Chartered Semiconductor Maunfacturing Pte. Ltd. Litigation, Intellectual Property, Attorneys, SEC Filings, and Other Public Records

Date Recorded	Party	Role	Document Type	Document No.	Invention Title

11/18/2020	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	11676522 20080197513 7847402	Beol Interconnect Structures With Improved Resistance To Stress Beol Interconnect Structures With Improved Resistance To Stress Beol Interconnect Structures With Improved Resistance To Stress

11/18/2020	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Application Application Application Publication Publication Publication Publication Patent Patent Patent Patent	11305584 11683590 11683648 12366356 20070138570 20080220584 20080220609 20100197093 7718500 7541288 7541290 7935593	Stress Optimization In Dual Embedded Epitaxially Grown Semiconductor Pro... Methods Of Forming Mask Patterns On Semiconductor Wafers That Compensate... Methods Of Forming Integrated Circuit Structures Using Insulator Deposit... Formation Of Raised Source/drain Structures In Nfet With Embedded Sige I... Stress Optimization In Dual Embedded Epitaxially Grown Semiconductor Pro... Methods Of Forming Mask Patterns On Semiconductor Wafers That Compensate... Methods Of Forming Integrated Circuit Structures Using Insulator Deposit... Formation Of Raised Source/drain Structures In Nfet With Embedded Sige I... Stress Optimization In Dual Embedded Epitaxially Grown Semiconductor Pro... Methods Of Forming Mask Patterns On Semiconductor Wafers That Compensate... Methods Of Forming Integrated Circuit Structures Using Insulator Deposit... Formation Of Raised Source/drain Structures In Nfet With Embedded Sige I...

11/18/2020	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Application Application Application Application Application Application Application Application Application Application Publication Publication Publication Publication Publication Publication Publication Publication Publication Publication Patent Patent Patent Patent Patent Patent ...and 7 more	10973526 11304455 11383951 11615980 11855168 09186388 10361934 11128010 10628913 11174857 10662674 20040157397 20050208712 20050023608 20060014336 20050059194 20060088771 20070138564 20070267703 20080150037 20090072310 6982215 6924180 6998682 6905919 7141854 6927104 ...and 7 more	Semiconductor Structure Including High Voltage Device Method Of Forming Double-gated Silicon-on-insulator (soi) Transistors Wi... Selective Sti Stress Relaxation Through Ion Implantation Double-gated Silicon-on-insulator (soi) Transistors With Corner Rounding Strained Channel Transistor And Method Of Fabrication Thereof Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Double Anneal With Improved Reliability For Dual Contact Etch Stop Liner... Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Anti-reflective Sidewall Coated Alternating Phase Shift Mask And Fabrica... Method Of Forming A Pocket Implant Region After Formation Of Composite I... Semiconductor Structure Including High Voltage Device Method Of Forming Double-gated Silicon-on-insulator (soi) Transistors Wi... Selective Sti Stress Relaxation Through Ion Implantation Double-gated Silicon-on-insulator (soi) Transistors With Corner Rounding Strained Channel Transistor And Method Of Fabrication Thereof Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Double Anneal With Improved Reliability For Dual Contact Etch Stop Liner... Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Anti-reflective Sidewall Coated Alternating Phase Shift Mask And Fabrica... Method Of Forming A Pocket Implant Region After Formation Of Composite I... Method Of Forming Double-gated Silicon-on-insulator (soi) Transistors Wi... N Type Impurity Doping Using Implantation Of P2+ Ions Or As2+ Ions Semiconductor Structure Including High Voltage Device Double-gated Silicon-on-insulator (soi) Transistors With Corner Rounding Selective Sti Stress Relaxation Through Ion Implantation Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Strained Channel Transistor And Method Of Fabrication Thereof ...and 7 more

11/17/2020	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	11676522 20080197513 7847402	Beol Interconnect Structures With Improved Resistance To Stress Beol Interconnect Structures With Improved Resistance To Stress Beol Interconnect Structures With Improved Resistance To Stress

11/17/2020	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Application Application Application Publication Publication Publication Publication Patent Patent Patent Patent	11305584 11683590 11683648 12366356 20070138570 20080220584 20080220609 20100197093 7718500 7541288 7541290 7935593	Stress Optimization In Dual Embedded Epitaxially Grown Semiconductor Pro... Methods Of Forming Mask Patterns On Semiconductor Wafers That Compensate... Methods Of Forming Integrated Circuit Structures Using Insulator Deposit... Formation Of Raised Source/drain Structures In Nfet With Embedded Sige I... Stress Optimization In Dual Embedded Epitaxially Grown Semiconductor Pro... Methods Of Forming Mask Patterns On Semiconductor Wafers That Compensate... Methods Of Forming Integrated Circuit Structures Using Insulator Deposit... Formation Of Raised Source/drain Structures In Nfet With Embedded Sige I... Stress Optimization In Dual Embedded Epitaxially Grown Semiconductor Pro... Methods Of Forming Mask Patterns On Semiconductor Wafers That Compensate... Methods Of Forming Integrated Circuit Structures Using Insulator Deposit... Formation Of Raised Source/drain Structures In Nfet With Embedded Sige I...

11/17/2020	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Application Application Application Application Application Application Application Application Application Application Publication Publication Publication Publication Publication Publication Publication Publication Publication Publication Patent Patent Patent Patent Patent Patent ...and 7 more	10662674 10973526 11304455 11383951 11615980 11855168 09186388 10361934 11128010 10628913 11174857 20090072310 20040157397 20050208712 20050023608 20060014336 20050059194 20060088771 20070138564 20070267703 20080150037 6982215 6924180 6998682 6905919 7141854 6927104 ...and 7 more	Double-gated Silicon-on-insulator (soi) Transistors With Corner Rounding Selective Sti Stress Relaxation Through Ion Implantation Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Strained Channel Transistor And Method Of Fabrication Thereof Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Double Anneal With Improved Reliability For Dual Contact Etch Stop Liner... Method Of Forming A Pocket Implant Region After Formation Of Composite I... Anti-reflective Sidewall Coated Alternating Phase Shift Mask And Fabrica... Method Of Forming Double-gated Silicon-on-insulator (soi) Transistors Wi... Semiconductor Structure Including High Voltage Device Double-gated Silicon-on-insulator (soi) Transistors With Corner Rounding Selective Sti Stress Relaxation Through Ion Implantation Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Strained Channel Transistor And Method Of Fabrication Thereof Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Double Anneal With Improved Reliability For Dual Contact Etch Stop Liner... Method Of Forming A Pocket Implant Region After Formation Of Composite I... Anti-reflective Sidewall Coated Alternating Phase Shift Mask And Fabrica... N Type Impurity Doping Using Implantation Of P2+ Ions Or As2+ Ions Method Of Forming Double-gated Silicon-on-insulator (soi) Transistors Wi... Double-gated Silicon-on-insulator (soi) Transistors With Corner Rounding Semiconductor Structure Including High Voltage Device Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Selective Sti Stress Relaxation Through Ion Implantation Method Of Forming A Partially Depleted Silicon On Insulator (pdsoi) Tran... Strained Channel Transistor And Method Of Fabrication Thereof Method Of Forming A Pocket Implant Region After Formation Of Composite I... ...and 7 more

11/20/2018	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Publication Publication Publication ...and 47 more	10690998 11358934 10689923 11299542 10688047 11930230 11160624 11122667 11039429 10913214 11029835 10778293 11034952 11029881 11972809 11174805 11614961 11161722 12247479 11462846 11465793 11481213 12048994 11421047 20060160343 20060030095 20060148270 ...and 47 more	Integrated Circuit With Protected Implantation Profiles And Method For T... Integrated Circuit System Employing Stress-engineered Spacers Composite Stress Spacer Method For Reducing Argon Diffusion From High Density Plasma Films Method Of Integrating Triple Gate Oxide Thickness Integrated Circuit System Employing Gate Shield And/or Ground Shield Integrated Circuit System Using Dual Damascene Process Method To Form A Contact Hole End Of Range (eor) Secondary Defect Engineering Using Chemical Vapor Dep... Method To Enhance Device Performance With Selective Stress Relief Integrated Circuit System Employing Backside Energy Source For Electrica... End Of Range (eor) Secondary Defect Engineering Using Substitutional Car... High Density Plasma And Bias Rf Power Process To Make Stable Fsg With Le... A Method For Using A Cu Beol Process To Fabricate An Integrated Circuit ... Method To Enhance Device Performance With Selective Stress Relief Method Of Manufacture Of An Integrated Circuit System With Self-aligned ... Integrated Circuit With Protected Implantation Profiles And Method For T... Methods For Elimination Of Arsenic Based Defects In Semiconductor Device... Method To Fabricate Aligned Dual Damacene Openings Entire Encapsulation Of Cu Interconnects Using Self-aligned Cusin Film Integrated Circuit System Employing Multiple Exposure Dummy Patterning T... Method To Fabricate Aligned Dual Damascene Openings Laser Activation Of Implanted Contact Plug For Memory Bitline Fabricatio... Method For Cuo Reduction By Using Two Step Nitrogen Oxygen And Reducing ... Integrated Circuit With Protected Implantation Profiles And Method For T... Integrated Circuit System Employing Stress-engineered Spacers Composite Stress Spacer ...and 47 more

3/15/2016	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	10923123 20060040491 9318378	Slot designs in wide metal lines Slot designs in wide metal lines Slot designs in wide metal lines

3/15/2016	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	10923123 20060040491 9318378	Slot designs in wide metal lines Slot designs in wide metal lines Slot designs in wide metal lines

1/27/2016	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	13286224 20120043659 9281278	Interconnects With Improved Tddb Interconnects With Improved Tddb Interconnects With Improved Tddb

1/27/2016	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	13286224 20120043659 9281278	Interconnects With Improved Tddb Interconnects With Improved Tddb Interconnects With Improved Tddb

1/13/2016	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	11683655 20070210376 9269770	Integrated Circuit System With Double Doped Drain Transistor Integrated Circuit System With Double Doped Drain Transistor Integrated Circuit System With Double Doped Drain Transistor

1/13/2016	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	11683655 20070210376 9269770	Integrated Circuit System With Double Doped Drain Transistor Integrated Circuit System With Double Doped Drain Transistor Integrated Circuit System With Double Doped Drain Transistor

3/1/2015	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	12133375 20090302391 8999863	Stress Liner For Stress Engineering Stress Liner For Stress Engineering Stress Liner For Stress Engineering

3/1/2015	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	12133375 20090302391 8999863	Stress Liner For Stress Engineering Stress Liner For Stress Engineering Stress Liner For Stress Engineering

1/23/2015	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	12040761 20090221117 8969151	Integrated Circuit System Employing Resistance Altering Techniques Integrated Circuit System Employing Resistance Altering Techniques Integrated Circuit System Employing Resistance Altering Techniques

1/23/2015	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	12040761 20090221117 8969151	Integrated Circuit System Employing Resistance Altering Techniques Integrated Circuit System Employing Resistance Altering Techniques Integrated Circuit System Employing Resistance Altering Techniques

11/13/2014	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	12396441 20100221926 8912102	Laser Annealing Laser Annealing Laser Annealing

11/13/2014	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	12396441 20100221926 8912102	Laser Annealing Laser Annealing Laser Annealing

4/27/2014	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	12857543 20100308374 8754447	Strained Channel Transistor Structure And Method Strained Channel Transistor Structure And Method Strained Channel Transistor Structure And Method

4/27/2014	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	12857543 20100308374 8754447	Strained Channel Transistor Structure And Method Strained Channel Transistor Structure And Method Strained Channel Transistor Structure And Method

3/9/2014	Globalfoundries Singapore Pte. Ltd.Â	Assignee	Application Publication Patent	11686475 20080224228 8716081	Capacitor Top Plate Over Source/drain To Form A 1t Memory Device Capacitor Top Plate Over Source/drain To Form A 1t Memory Device Capacitor Top Plate Over Source/drain To Form A 1t Memory Device

3/9/2014	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	11686475 20080224228 8716081	Capacitor Top Plate Over Source/drain To Form A 1t Memory Device Capacitor Top Plate Over Source/drain To Form A 1t Memory Device Capacitor Top Plate Over Source/drain To Form A 1t Memory Device

3/3/2014	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	12147489 20090326996 8712569	Lot Handling During Manufacturing System For Determining Potential Lot Consolidation During Manufacturing Lot Handling During Manufacturing

3/3/2014	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	12147489 20090326996 8712569	Lot Handling During Manufacturing System For Determining Potential Lot Consolidation During Manufacturing Lot Handling During Manufacturing

1/22/2014	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	12125030 20090291311 8668833	Method Of Forming A Nanostructure Method Of Forming A Nanostructure Method Of Forming A Nanostructure

1/22/2014	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	12125030 20090291311 8668833	Method Of Forming A Nanostructure Method Of Forming A Nanostructure Method Of Forming A Nanostructure

12/3/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Application	13366355 20120139046 8629503	Asymmetrical Transistor Device And Method Of Fabrication Asymmetrical Transistor Device And Method Of Fabrication

12/3/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Application	13366355 20120139046 8629503	Asymmetrical Transistor Device And Method Of Fabrication Asymmetrical Transistor Device And Method Of Fabrication

11/27/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Application	12613541 20100059831 8624329	Spacer-less Low-k Dielectric Processes Spacer-less Low-k Dielectric Processes

11/27/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Application	12613541 20100059831 8624329	Spacer-less Low-k Dielectric Processes Spacer-less Low-k Dielectric Processes

9/25/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	11943591 20090132992 8572524	Statistical Optical Proximity Correction Statistical Optical Proximity Correction Statistical Optical Proximity Correction

9/25/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	11943591 20090132992 8572524	Statistical Optical Proximity Correction Statistical Optical Proximity Correction Statistical Optical Proximity Correction

8/27/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	13241215 20120012940 8546873	Integrated Circuit And Method Of Fabrication Thereof Integrated Circuit And Method Of Fabrication Thereof Integrated Circuit And Method Of Fabrication Thereof

8/27/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	13241215 20120012940 8546873	Integrated Circuit And Method Of Fabrication Thereof Integrated Circuit And Method Of Fabrication Thereof Integrated Circuit And Method Of Fabrication Thereof

8/14/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	13455152 20120205806 8536705	Integrated Circuit System With Through Silicon Via And Method Of Manufac... Integrated Circuit System With Through Silicon Via And Method Of Manufac... Integrated Circuit System With Through Silicon Via And Method Of Manufac...

8/14/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	13455152 20120205806 8536705	Integrated Circuit System With Through Silicon Via And Method Of Manufac... Integrated Circuit System With Through Silicon Via And Method Of Manufac... Integrated Circuit System With Through Silicon Via And Method Of Manufac...

7/21/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	13182455 20110266628 8519445	Poly Profile Engineering To Modulate Spacer Induced Stress For Device En... Poly Profile Engineering To Modulate Spacer Induced Stress For Device En... Poly Profile Engineering To Modulate Spacer Induced Stress For Device En...

7/21/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	13182455 20110266628 8519445	Poly Profile Engineering To Modulate Spacer Induced Stress For Device En... Poly Profile Engineering To Modulate Spacer Induced Stress For Device En... Poly Profile Engineering To Modulate Spacer Induced Stress For Device En...

7/1/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	13550571 20120280318 8507983	High Voltage Device High Voltage Device High Voltage Device

7/1/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	13550571 20120280318 8507983	High Voltage Device High Voltage Device High Voltage Device

4/28/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	11696732 20080246119 8450832	Large Tuning Range Junction Varactor Large Tuning Range Junction Varactor Large Tuning Range Junction Varactor

4/28/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	11696732 20080246119 8450832	Large Tuning Range Junction Varactor Large Tuning Range Junction Varactor Large Tuning Range Junction Varactor

4/22/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	12392093 20090214984 8450046	Methods For Enhancing Photolithography Patterning Methods For Enhancing Photolithography Patterning Methods For Enhancing Photolithography Patterning

4/22/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	12392093 20090214984 8450046	Methods For Enhancing Photolithography Patterning Methods For Enhancing Photolithography Patterning Methods For Enhancing Photolithography Patterning

3/26/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	13229773 20120001228 8450775	Method To Control Source/drain Stressor Profiles For Stress Engineering Method To Control Source/drain Stressor Profiles For Stress Engineering Method To Control Source/drain Stressor Profiles For Stress Engineering

3/26/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	13229773 20120001228 8450775	Method To Control Source/drain Stressor Profiles For Stress Engineering Method To Control Source/drain Stressor Profiles For Stress Engineering Method To Control Source/drain Stressor Profiles For Stress Engineering

3/20/2013	Chartered Semiconductor Manufacturing Lt...	Assignor	Application Publication Patent	12648309 20100167505 8415236	Methods For Reducing Loading Effects During Film Formation Methods For Reducing Loading Effects During Film Formation Methods For Reducing Loading Effects During Film Formation

3/20/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	12648309 20100167505 8415236	Methods For Reducing Loading Effects During Film Formation Methods For Reducing Loading Effects During Film Formation Methods For Reducing Loading Effects During Film Formation

3/2/2013	Globalfoundries Singapore Pte. Ltd.	Assignee	Application Publication Patent	12964753 20110079850 8410553	Semiconductor Structure Including High Voltage Device Semiconductor Structure Including High Voltage Device Semiconductor Structure Including High Voltage Device

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