Micron Technology, Inc. Litigation, Intellectual Property, Attorneys, SEC Filings, and Other Public Records

Date Recorded	Party	Role	Document Type	Document No.	Invention Title

5/13/2025	Kim, Jeonghun	Assignor	Application Publication	18937737 20250147669	Incremental Power Throttling On Memory System Incremental Power Throttling On Memory System

5/13/2025	Rajgopal, Suresh	Assignor	Application Publication	18937737 20250147669	Incremental Power Throttling On Memory System Incremental Power Throttling On Memory System

5/13/2025	Byron, Brent Carl	Assignor	Application Publication	18937737 20250147669	Incremental Power Throttling On Memory System Incremental Power Throttling On Memory System

5/13/2025	Bukhari, Shakeel	Assignor	Application Publication	18937737 20250147669	Incremental Power Throttling On Memory System Incremental Power Throttling On Memory System

5/12/2025	Lodestar Licensing Group LLC	Assignee	Application Application Application Application Publication Publication Publication Publication Patent Patent Patent	18652714 18200439 17372453 16509417 20230297472 20210334159 20200019462 20240289219 11977444 11698831 11074126	Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A... Methods For Error Count Reporting With Scaled Error Count Information, A...

5/9/2025	Mcdaniel, Terrence B.	Assignor	Application Publication	18660210 20240379596	Conductive Pad On A Through-silicon Via Conductive Pad On A Through-silicon Via

5/9/2025	Bhushan, Bharat	Assignor	Application Publication	18660210 20240379596

5/9/2025	Parekh, Kunal R.	Assignor	Application Publication	18660210 20240379596

5/9/2025	Street, Bret K.	Assignor	Application Publication	18660210 20240379596

5/9/2025	Singh, Akshay N.	Assignor	Application Publication	18660210 20240379596

5/8/2025	He, Deping	Assignor	Application Publication	18776201 20250117150	Data Transfer During Maintenance Operations Data Transfer During Maintenance Operations

5/8/2025	Grosz, Nadav	Assignor	Application Publication	18776201 20250117150	Data Transfer During Maintenance Operations Data Transfer During Maintenance Operations

5/8/2025	Wang, Zheng	Assignor	Application Publication	18492569 20240160386	Variable Density Storage Device Variable Density Storage Device

5/8/2025	Ramamoorthy, Aravind	Assignor	Application Publication	18492569 20240160386	Variable Density Storage Device Variable Density Storage Device

5/8/2025	Duval, Olivier	Assignor	Application Publication	18492569 20240160386	Variable Density Storage Device Variable Density Storage Device

5/8/2025	Bueb, Christopher Joseph	Assignor	Application Publication	18492569 20240160386	Variable Density Storage Device Variable Density Storage Device

5/8/2025	Mudlapur, Anand	Assignor	Application Publication	18492569 20240160386	Variable Density Storage Device Variable Density Storage Device

5/8/2025	Mazumder, Kallol	Assignor	Application Publication	18478893 20240168678	Techniques For Performing Write Operations Techniques For Performing Write Operations

5/8/2025	Kandikonda	Assignor	Application Publication	18478893 20240168678	Techniques For Performing Write Operations Techniques For Performing Write Operations

5/6/2025	Lodestar Licensing Group LLC	Assignee	Application Application Publication Publication Patent	17223359 18505563 20240081052 20220320129 11856764	Memory Arrays Comprising Strings Of Memory Cells And Methods Used In For... Memory Arrays Comprising Strings Of Memory Cells And Methods Used In For... Memory Arrays Comprising Strings Of Memory Cells And Methods Used In For... Memory Arrays Comprising Strings Of Memory Cells And Methods Used In For... Memory Arrays Comprising Strings Of Memory Cells And Methods Used In For...

5/2/2025	Lodestar Licensing Group LLC	Assignee	Application Application Application Publication Publication Publication Patent Patent	18407963 17943574 17150849 20230006816 20220231839 20240146525 11917059 11483148	Batch Transfer of Control of Memory Devices over Computer Networks Batch Transfer of Control of Memory Devices over Computer Networks Batch Transfer of Control of Memory Devices over Computer Networks Batch Transfer of Control of Memory Devices over Computer Networks Batch Transfer of Control of Memory Devices over Computer Networks Batch Transfer of Control of Memory Devices over Computer Networks Batch Transfer of Control of Memory Devices over Computer Networks Batch Transfer of Control of Memory Devices over Computer Networks

5/2/2025	Dover, Lance W.	Assignor	Application Publication	18407963 20240146525

5/2/2025	Nelson, Travis Duane	Assignor	Application Publication	18407963 20240146525

4/30/2025	Balasubramani, Muthazhagan	Assignor	Application Publication	19005870 20250130949	Latency Reduction Using Stream Cache Latency Reduction Using Stream Cache

4/30/2025	Anandpadmanabhan, Venkatesh	Assignor	Application Publication	19005870 20250130949	Latency Reduction Using Stream Cache Latency Reduction Using Stream Cache

4/28/2025	Lodestar Licensing Group LLC	Assignee	Application Application Publication Publication Patent	16839371 18667099 20240304269 20210202023 11468960	Semiconductor Device With Selective Command Delay And Associated Methods... Semiconductor Device With Selective Command Delay And Associated Methods... Semiconductor Device With Selective Command Delay And Associated Methods... Semiconductor Device With Selective Command Delay And Associated Methods... Semiconductor Device With Selective Command Delay And Associated Methods...

4/25/2025	Huang, Jianmin	Assignor	Application Publication	18788730 20250104799	Mixed-mode Virtual Block Generation Mixed-mode Virtual Block Generation

4/25/2025	Luo, Xiangang	Assignor	Application Publication	18788730 20250104799	Mixed-mode Virtual Block Generation Mixed-mode Virtual Block Generation

4/25/2025	Hu, Guang	Assignor	Application Publication	18788730 20250104799	Mixed-mode Virtual Block Generation Mixed-mode Virtual Block Generation

4/25/2025	Dover, Lance W.	Assignor	Application Publication	18221790 20240073002	Generating A Shared Secret For An Electronic System Generating A Shared Secret For An Electronic System

4/25/2025	Ramaswamy, Durai Vishak Nirmal	Assignor	Application Publication	18778321 20250029638	Memory Device Including 2-transistor Memory Cell Structure For Neural Ne... Memory Device Including 2-transistor Memory Cell Structure For Neural Ne...

4/25/2025	Karda, Kamal M.	Assignor	Application Publication	18778321 20250029638	Memory Device Including 2-transistor Memory Cell Structure For Neural Ne... Memory Device Including 2-transistor Memory Cell Structure For Neural Ne...

4/25/2025	Sarpatwari, Karthik	Assignor	Application Publication	18778321 20250029638	Memory Device Including 2-transistor Memory Cell Structure For Neural Ne... Memory Device Including 2-transistor Memory Cell Structure For Neural Ne...

4/25/2025	Calderoni, Alessandro	Assignor	Application Publication	18778321 20250029638	Memory Device Including 2-transistor Memory Cell Structure For Neural Ne... Memory Device Including 2-transistor Memory Cell Structure For Neural Ne...

4/25/2025	Gao, Yunfei	Assignor	Application Publication	18778321 20250029638	Memory Device Including 2-transistor Memory Cell Structure For Neural Ne... Memory Device Including 2-transistor Memory Cell Structure For Neural Ne...

4/24/2025	Brown, David R.	Assignor	Application Application Application Publication Publication Publication Patent Patent Patent	15262958 15871660 16917221 20160379114 20180137416 20200334533 9870530 10733508 11977977	Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine

4/24/2025	Noyes, Harold B.	Assignor	Application Application Application Publication Publication Publication Patent Patent Patent	15262958 15871660 16917221 20160379114 20180137416 20200334533 9870530 10733508 11977977	Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine Methods And Systems For Data Analysis In A State Machine

4/24/2025	Brown, David R.	Assignor	Application Application Application Publication Publication Publication Patent Patent Patent	15605542 14722941 14143398 20170261956 20150253755 20140115299 9886017 9665083 9058465	Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice

4/24/2025	Noyes, Harold B.	Assignor	Application Application Application Publication Publication Publication Patent Patent Patent	15605542 14722941 14143398 20170261956 20150253755 20140115299 9058465 9886017 9665083	Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice

4/24/2025	Glendenning, Paul	Assignor	Application Application Application Publication Publication Publication Patent Patent Patent	15605542 14722941 14143398 20170261956 20150253755 20140115299 9886017 9665083 9058465	Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice Counter Operation In A State Machine Lattice

4/24/2025	Brown, David R.	Assignor	Application Application Publication Publication Patent Patent	14329586 15063230 20140325494 20160188346 9280329 9817678	Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine

4/24/2025	Noyes, Harold B.	Assignor	Application Application Publication Publication Patent Patent	14329586 15063230 20140325494 20160188346 9280329 9817678	Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine Methods And Systems For Detection In A State Machine

4/24/2025	Wu, Wenjun	Assignor	Application Publication	18771713 20250117321	Compression-based Address Mapping Management In A Memory System Compression-based Address Mapping Management In A Memory System

4/24/2025	He, Deping	Assignor	Application Publication	18771713 20250117321	Compression-based Address Mapping Management In A Memory System Compression-based Address Mapping Management In A Memory System

4/23/2025	Lodestar Licensing Group LLC	Assignee	Application Application Application Publication Publication Patent Patent	17495410 16869397 18662743 20220100674 20240296125 11144471 11704252	Dual Address Encoding For Logical-to-physical Mapping Dual Address Encoding For Logical-to-physical Mapping Dual Address Encoding For Logical-to-physical Mapping Dual Address Encoding For Logical-to-physical Mapping Dual Address Encoding For Logical-to-physical Mapping Dual Address Encoding For Logical-to-physical Mapping Dual Address Encoding For Logical-to-physical Mapping

4/23/2025	Lodestar Licensing Group, LLC	Assignee	Application Publication	18134318 20230335166	Memory Devices Having Special Mode Access Memory Devices Having Special Mode Access

4/22/2025	Mcneil, Jeffrey S.	Assignor	Application Publication	18214080 20240005987	Establishing Bitline, Wordline And Boost Voltages To Manage A Maximum Pr... Establishing Bitline, Wordline And Boost Voltages To Manage A Maximum Pr...

4/22/2025	Iwasaki, Tomoko Ogura	Assignor	Application Publication	18214080 20240005987	Establishing Bitline, Wordline And Boost Voltages To Manage A Maximum Pr... Establishing Bitline, Wordline And Boost Voltages To Manage A Maximum Pr...

4/22/2025	Ning, Sheyang	Assignor	Application Publication	18214080 20240005987	Establishing Bitline, Wordline And Boost Voltages To Manage A Maximum Pr... Establishing Bitline, Wordline And Boost Voltages To Manage A Maximum Pr...

4/22/2025	Miranda, Lawrence Celso	Assignor	Application Publication	18214080 20240005987	Establishing Bitline, Wordline And Boost Voltages To Manage A Maximum Pr... Establishing Bitline, Wordline And Boost Voltages To Manage A Maximum Pr...

4/17/2025	Lodestar Licensing Group LLC	Assignee	Application Application Publication Publication Patent	15684773 18673276 20190065105 20240311055 11210019	Memory With Virtual Page Size Memory With Virtual Page Size Memory With Virtual Page Size Memory With Virtual Page Size Memory With Virtual Page Size

4/17/2025	Lodestar Licensing Group LLC	Assignee	Application Application Application Publication Publication Publication Patent Patent	15466296 17543498 18471890 20180276539 20220092422 20240242074 11222260 11769053	Apparatuses And Methods For Operating Neural Networks Apparatuses And Methods For Operating Neural Networks Apparatuses And Methods For Operating Neural Networks Apparatuses And Methods For Operating Neural Networks Apparatuses And Methods For Operating Neural Networks Apparatuses And Methods For Operating Neural Networks Apparatuses And Methods For Operating Neural Networks Apparatuses And Methods For Operating Neural Networks

4/15/2025	Kim, Junam	Assignor	Application Publication	18444064 20240281158	Techniques For Memory System Standby Mode Control Techniques For Memory System Standby Mode Control

4/15/2025	Bi, Yanhua	Assignor	Application Publication	18441945 20240281373	Memory System Host Data Reset Function Memory System Host Data Reset Function

4/10/2025	Nguyen, Dung Viet	Assignor	Application Publication	18781970 20250103238	Modulation Code Permutation Selection For Data Modulation In Memory Syst... Modulation Code Permutation Selection For Data Modulation In Memory Syst...

4/10/2025	Nguyen, Phong S.	Assignor	Application Publication	18781970 20250103238	Modulation Code Permutation Selection For Data Modulation In Memory Syst... Modulation Code Permutation Selection For Data Modulation In Memory Syst...

4/7/2025	Yarragunta, Suresh Reddy	Assignor	Application Publication	18204704 20240107657	Memory Sub-system Enclosure Memory Sub-system Enclosure

4/7/2025	Subhash, Deepu Narasimiah	Assignor	Application Publication	18204704 20240107657	Memory Sub-system Enclosure Memory Sub-system Enclosure

4/7/2025	Kollipara, Ravi Kumar	Assignor	Application Publication	18204704 20240107657	Memory Sub-system Enclosure Memory Sub-system Enclosure

4/4/2025	Onorato, Marco	Assignor	Application Publication	18520387 20240176549	Latency Reduction Of Boot Procedures For Memory Systems Latency Reduction Of Boot Procedures For Memory Systems

4/4/2025	Zucchinali, Massimo	Assignor	Application Publication	18520387 20240176549	Latency Reduction Of Boot Procedures For Memory Systems Latency Reduction Of Boot Procedures For Memory Systems

4/4/2025	Porzio, Luca	Assignor	Application Publication	18520387 20240176549	Latency Reduction Of Boot Procedures For Memory Systems Latency Reduction Of Boot Procedures For Memory Systems

4/4/2025	Izzi, Roberto	Assignor	Application Publication	18520387 20240176549	Latency Reduction Of Boot Procedures For Memory Systems Latency Reduction Of Boot Procedures For Memory Systems

4/4/2025	Manion, Sean L.	Assignor	Application Publication	18520387 20240176549	Latency Reduction Of Boot Procedures For Memory Systems Latency Reduction Of Boot Procedures For Memory Systems

4/4/2025	Vigilante, Andrea	Assignor	Application Publication	18520387 20240176549	Latency Reduction Of Boot Procedures For Memory Systems Latency Reduction Of Boot Procedures For Memory Systems

4/4/2025	Butler, Bryan D.	Assignor	Application Publication	18520387 20240176549	Latency Reduction Of Boot Procedures For Memory Systems Latency Reduction Of Boot Procedures For Memory Systems

4/4/2025	Palazzo, Alfredo	Assignor	Application Publication	18520387 20240176549	Latency Reduction Of Boot Procedures For Memory Systems Latency Reduction Of Boot Procedures For Memory Systems

4/2/2025	Lodestar Licensing Group LLC	Assignee	Application Application Application Application Publication Publication Publication Patent Patent Patent	16716947 17208868 17720223 18827561 20210288071 20220238554 20240431110 10978478 11335700 12114499	Block-on-block Memory Array Architecture Using Bi-directional Staircases Block-on-block Memory Array Architecture Using Bi-directional Staircases Block-on-block Memory Array Architecture Using Bi-directional Staircases Block-on-block Memory Array Architecture Using Bi-directional Staircases Block-on-block Memory Array Architecture Using Bi-directional Staircases Block-on-block Memory Array Architecture Using Bi-directional Staircases Block-on-block Memory Array Architecture Using Bi-directional Staircases Block-on-block Memory Array Architecture Using Bi-directional Staircases Block-on-block Memory Array Architecture Using Bi-directional Staircases Block-on-block Memory Array Architecture Using Bi-directional Staircases

4/2/2025	Yip, Aaron S.	Assignor	Application Publication	18827561 20240431110

4/2/2025	Parthasarathy, Sivagnanam	Assignor	Application Publication	18830272 20240428858	Managing Compensation For Cell-to-cell Coupling And Lateral Migration In... Managing Compensation For Cell-to-cell Coupling And Lateral Migration In...

4/2/2025	Kaynak, Mustafa N.	Assignor	Application Publication	18830272 20240428858	Managing Compensation For Cell-to-cell Coupling And Lateral Migration In... Managing Compensation For Cell-to-cell Coupling And Lateral Migration In...

4/2/2025	Khayat, Patrick R.	Assignor	Application Publication	18830272 20240428858	Managing Compensation For Cell-to-cell Coupling And Lateral Migration In... Managing Compensation For Cell-to-cell Coupling And Lateral Migration In...

4/2/2025	Mcneil, Jeffrey S.	Assignor	Application Publication	18806444 20240402922	Two-tier Defect Scan Management Two-tier Defect Scan Management

4/2/2025	Lee, Eric N.	Assignor	Application Publication	18806444 20240402922	Two-tier Defect Scan Management Two-tier Defect Scan Management

4/2/2025	Muchherla, Kishore Kumar	Assignor	Application Publication	18806444 20240402922	Two-tier Defect Scan Management Two-tier Defect Scan Management

4/2/2025	Parry, Jonathan S.	Assignor	Application Publication	18806444 20240402922	Two-tier Defect Scan Management Two-tier Defect Scan Management

4/2/2025	Zildzic, Sead	Assignor	Application Publication	18806444 20240402922	Two-tier Defect Scan Management Two-tier Defect Scan Management

4/2/2025	Vakati, Lakshmi Kalpana K.	Assignor	Application Publication	18806444 20240402922	Two-tier Defect Scan Management Two-tier Defect Scan Management

4/2/2025	Ursua, Robert Loren O.	Assignor	Application Publication	18806444 20240402922	Two-tier Defect Scan Management Two-tier Defect Scan Management

4/1/2025	Lodestar Licensing Group LLC	Assignee	Application Publication	18795728 20240396746	Cryptographically Secure Mechanism For Remotely Controlling An Autonomou... Cryptographically Secure Mechanism For Remotely Controlling An Autonomou...

4/1/2025	Mondello, Antonino	Assignor	Application Publication	18795728 20240396746

4/1/2025	Troia, Alberto	Assignor	Application Publication	18795728 20240396746

3/31/2025	Parthasarathy, Sivagnanam	Assignor	Application Publication	18975874 20250103218	Managing Error Compensation Using Charge Coupling And Lateral Migration ... Managing Error Compensation Using Charge Coupling And Lateral Migration ...

3/31/2025	Kaynak, Mustafa N.	Assignor	Application Publication	18975874 20250103218	Managing Error Compensation Using Charge Coupling And Lateral Migration ... Managing Error Compensation Using Charge Coupling And Lateral Migration ...

3/31/2025	Khayat, Patrick R.	Assignor	Application Publication	18975874 20250103218	Managing Error Compensation Using Charge Coupling And Lateral Migration ... Managing Error Compensation Using Charge Coupling And Lateral Migration ...

3/28/2025	Lodestar Licensing Group LLC	Assignee	Application Application Publication Publication Patent	15066831 18587207 20170263306 20240194247 9997232	Processing In Memory (pim) Capable Memory Device Having Sensing Circuitr... Apparatuses And Methods For Logic/memory Devices Apparatuses And Methods For Logic/memory Devices Apparatuses And Methods For Logic/memory Devices Apparatuses And Methods For Logic/memory Devices

3/25/2025	Dubey, Rishabh	Assignor	Application Publication	18781982 20250130937	Address Translation In A Memory Sub-system For Memory Pooling Address Translation In A Memory Sub-system For Memory Pooling

3/24/2025	Siluvainathan, Melky Arputharaja	Assignor	Application Publication	18781989 20250061065	Configuring Pci Express Module Using Hardware In A Memory Sub-system Configuring Pci Express Module Using Hardware In A Memory Sub-system

3/21/2025	Kim, Hyungseok	Assignor	Application Publication	18661526 20240385926	Temperature Sensor Management During Error Handling Operations In A Memo... Temperature Sensor Management During Error Handling Operations In A Memo...

3/21/2025	Kientz, Steven Michael	Assignor	Application Publication	18661526 20240385926	Temperature Sensor Management During Error Handling Operations In A Memo... Temperature Sensor Management During Error Handling Operations In A Memo...

3/21/2025	Wan, Jun	Assignor	Application Publication	18661526 20240385926	Temperature Sensor Management During Error Handling Operations In A Memo... Temperature Sensor Management During Error Handling Operations In A Memo...

3/21/2025	Khayat, Patrick R.	Assignor	Application Publication	18661526 20240385926	Temperature Sensor Management During Error Handling Operations In A Memo... Temperature Sensor Management During Error Handling Operations In A Memo...

3/21/2025	Loh, Zixiang	Assignor	Application Publication	18661526 20240385926	Temperature Sensor Management During Error Handling Operations In A Memo... Temperature Sensor Management During Error Handling Operations In A Memo...

3/21/2025	Goda, Akira	Assignor	Application Publication	18407366 20240231642	Self-optimizing Corrective Read Offsets With Lateral Charge Migration Pr... Self-optimizing Corrective Read Offsets With Lateral Charge Migration Pr...

3/21/2025	Righetti, Niccolo	Assignor	Application Publication	18407366 20240231642	Self-optimizing Corrective Read Offsets With Lateral Charge Migration Pr... Self-optimizing Corrective Read Offsets With Lateral Charge Migration Pr...

3/21/2025	Nicosia, Gianluca	Assignor	Application Publication	18407366 20240231642	Self-optimizing Corrective Read Offsets With Lateral Charge Migration Pr... Self-optimizing Corrective Read Offsets With Lateral Charge Migration Pr...

3/14/2025	Wan, Jun	Assignor	Application Publication	18788550 20250117289	Valley Check Memory System Command Valley Check Memory System Command

3/14/2025	Jeon, Seungjune	Assignor	Application Publication	18788550 20250117289	Valley Check Memory System Command Valley Check Memory System Command

3/14/2025	Kwong, Charles S.	Assignor	Application Publication	18788550 20250117289	Valley Check Memory System Command Valley Check Memory System Command

3/12/2025	Lodestar Licensing Group LLC	Assignee	Application Application Application Application Publication Publication Publication Publication Patent Patent Patent Patent	11436169 10657081 10754801 10983934 20040046266 20040198367 20050098857 20060262164 6908857 7263364 7262489 7372477	Three-dimensionally Formed Circuit Sheet, Component And Method For Manuf... Data Communication Method For Mobile Communication System Method Of Manufacturing Semiconductor Device Thermal Head And Manufacturing Method Thereof Three-dimensionally Formed Circuit Sheet, Component And Method For Manuf... Data Communication Method For Mobile Communication System Method Of Manufacturing Semiconductor Device Thermal Head And Manufacturing Method Thereof Three-dimensionally Formed Circuit Sheet, Component And Method For Manuf... Data Communication Method For Mobile Communication System Method Of Manufacturing Semiconductor Device Thermal Head And Manufacturing Method Thereof

3/12/2025	Sarkar, Jay	Assignor	Application Publication	18905398 20250117137	Self-optimization Of Data Placement In Memory Or Storage Systems Self-optimization Of Data Placement In Memory Or Storage Systems

3/12/2025	Tehrani, Saeed Sharifi	Assignor	Application Publication	18905398 20250117137	Self-optimization Of Data Placement In Memory Or Storage Systems Self-optimization Of Data Placement In Memory Or Storage Systems

3/12/2025	Ebsen, David Scott	Assignor	Application Publication	18905398 20250117137	Self-optimization Of Data Placement In Memory Or Storage Systems Self-optimization Of Data Placement In Memory Or Storage Systems

3/12/2025	Karakulak, Seyhan	Assignor	Application Publication	18905398 20250117137	Self-optimization Of Data Placement In Memory Or Storage Systems Self-optimization Of Data Placement In Memory Or Storage Systems

3/12/2025	Lucas, Aaron	Assignor	Application Publication	18905398 20250117137	Self-optimization Of Data Placement In Memory Or Storage Systems Self-optimization Of Data Placement In Memory Or Storage Systems

3/12/2025	Sforzin, Marco	Assignor	Application Publication	18903468 20250130720	Wear Leveling Operations In Memory Devices Wear Leveling Operations In Memory Devices

3/12/2025	Confalonieri, Emanuele	Assignor	Application Publication	18903468 20250130720	Wear Leveling Operations In Memory Devices Wear Leveling Operations In Memory Devices

3/12/2025	Morzano, Christopher K.	Assignor	Application Publication	18777365 20250133719	Memory Device Having Hexagonal Memory Cells With Pillar Lattice Memory Device Having Hexagonal Memory Cells With Pillar Lattice

3/12/2025	Simsek-ege, Fatma Arzum	Assignor	Application Publication	18777365 20250133719	Memory Device Having Hexagonal Memory Cells With Pillar Lattice Memory Device Having Hexagonal Memory Cells With Pillar Lattice

3/12/2025	Ege, Efe Sinan	Assignor	Application Publication	18777365 20250133719	Memory Device Having Hexagonal Memory Cells With Pillar Lattice Memory Device Having Hexagonal Memory Cells With Pillar Lattice

3/7/2025	Stoller, Scott Anthony	Assignor	Application Publication	18637913 20240355402	Known-failure Error Handling In A Memory Sub-system Known-failure Error Handling In A Memory Sub-system

3/7/2025	Brock-petersen, Kyle	Assignor	Application Publication	18637913 20240355402	Known-failure Error Handling In A Memory Sub-system Known-failure Error Handling In A Memory Sub-system

3/7/2025	Mason, Robert Winston	Assignor	Application Publication	18637913 20240355402	Known-failure Error Handling In A Memory Sub-system Known-failure Error Handling In A Memory Sub-system

3/6/2025	Jain, Kaveri	Assignor	Application Publication	18750247 20250006655	Photoalignment Of Semiconductor Structures Using An Opaque Hardmask Photoalignment Of Semiconductor Structures Using An Opaque Hardmask

3/6/2025	Jain, Harsh Narendrakumar	Assignor	Application Publication	18750247 20250006655	Photoalignment Of Semiconductor Structures Using An Opaque Hardmask Photoalignment Of Semiconductor Structures Using An Opaque Hardmask

3/6/2025	Kumara Vadivel, Shruthi	Assignor	Application Publication	18750247 20250006655	Photoalignment Of Semiconductor Structures Using An Opaque Hardmask Photoalignment Of Semiconductor Structures Using An Opaque Hardmask

3/6/2025	Williamson, Lance David	Assignor	Application Publication	18750247 20250006655	Photoalignment Of Semiconductor Structures Using An Opaque Hardmask Photoalignment Of Semiconductor Structures Using An Opaque Hardmask

3/6/2025	Olson, Adam Lewis	Assignor	Application Publication	18750247 20250006655	Photoalignment Of Semiconductor Structures Using An Opaque Hardmask Photoalignment Of Semiconductor Structures Using An Opaque Hardmask

3/6/2025	Simsek-ege, Fatma Arzum	Assignor	Application Publication	18777396 20250133720	Memory Device Having Hexagonal Memory Cells Memory Device Having Hexagonal Memory Cells

3/6/2025	Ege, Efe Sinan	Assignor	Application Publication	18777396 20250133720	Memory Device Having Hexagonal Memory Cells Memory Device Having Hexagonal Memory Cells

3/5/2025	Liu, Yang	Assignor	Application Publication	18749234 20250022529	Block Health Detector For Block Retirement In A Memory Sub-system Block Health Detector For Block Retirement In A Memory Sub-system

3/5/2025	Shen, Zhenlei	Assignor	Application Publication	18749234 20250022529	Block Health Detector For Block Retirement In A Memory Sub-system Block Health Detector For Block Retirement In A Memory Sub-system

3/5/2025	Brandt, Kevin R.	Assignor	Application Publication	18749234 20250022529	Block Health Detector For Block Retirement In A Memory Sub-system Block Health Detector For Block Retirement In A Memory Sub-system

3/5/2025	Zhu, Jiangli	Assignor	Application Publication	18749234 20250022529	Block Health Detector For Block Retirement In A Memory Sub-system Block Health Detector For Block Retirement In A Memory Sub-system

3/5/2025	Wu, Fanqi	Assignor	Application Publication	18749234 20250022529	Block Health Detector For Block Retirement In A Memory Sub-system Block Health Detector For Block Retirement In A Memory Sub-system

3/5/2025	Xie, Tingjun	Assignor	Application Publication	18749234 20250022529	Block Health Detector For Block Retirement In A Memory Sub-system Block Health Detector For Block Retirement In A Memory Sub-system

126 Rows Total

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