Proebsting, Robert J. Litigation, Intellectual Property, Attorneys, SEC Filings, and Other Public Records

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Date Recorded	Party	Role	Document Type	Document No.	Invention Title

6/16/2008	Townsend And Townsend And Crew LLP	Assignor	Application Patent	08321390 5585747	High Speed Low Power Sense Amplifier High Speed Low Power Sense Amplifier

6/16/2008	Townsend And Townsend And Crew LLP	Assignor	Application Patent	08438148 5546338	Fast Voltage Equilibration Of Differential Data Lines Fast Voltage Equilibration Of Differential Data Lines

6/16/2008	Townsend And Townsend And Crew LLP	Assignor	Application Patent	08297723 5453951	Fast Voltage Equilibration Of Complementary Data Lines Following Write C... Fast Voltage Equilibration Of Complementary Data Lines Following Write C...

6/16/2008	Townsend And Townsend And Crew LLP	Assignor	Application Patent	08252284 5495445	Redundancy Scheme For Memory Circuits Redundancy Scheme For Memory Circuits

6/16/2008	Arlene H. Proebsting And Todd A. Proebst...	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Publication ...and 28 more	08630310 09502983 09287948 09516399 09503048 09329975 11085770 09439061 09999563 09474351 08321390 08656165 09503108 09199884 08297723 09503049 09372320 08252284 09499265 08630283 08890584 09503109 09285232 08438148 09503050 09451042 20050166009 ...and 28 more	Integrated Circuit Random Access Memory Capable Of Automatic Internal Re... Equilibration Circuit And Method Using A Pulsed Equilibrate Signal And A... Memory array having selected word lines driven to an internally-generate... Fast Voltage Equilibration Of Differential Data Lines Hierarchical Dynamic Memory Array Architecture Using Read Amplifiers Sep... Merging write cycles by comparing at least a portion of the respective w... Apparatus For Translating A Voltage Bit Line Cross-over Layout Arrangement Dynamic memory array bit line sense amplifier enabled to drive toward, b... Self Adjusting Delay Circuit And Method For Compensating Sense Amplifier... Disabling A Decoder For A Defective Element In An Integrated Circuit Dev... Integrated circuit random access memory capable of reading either one or... Word Line Driver Circuit Power Bussing Layout For Memory Circuits Word line straps using two differentlayers of metal Redundancy Scheme For Memory Circuits Integrated Circuit Random Access Memory Capable Of Automatic Internal Re... Equilibration Circuit And Method Using A Pulsed Equilibrate Signal And A... Memory array having selected word lines driven to an internally-generate... Fast Voltage Equilibration Of Differential Data Lines Dynamic Memory Array Having Write Data Applied To Selected Bit Line Sens... Intializing memory cells within a dynamic memory array prior to performi... Fast Voltage Equilibration Of Complementary Data Lines Following Write C... Bit Line Cross-over Layout Arrangement Dynamic memory array bit line sense amplifier enabled to drive toward, b... Self Adjusting Delay Circuit And Method For Compensating Sense Amplifier... Disabling A Defective Element In An Integrated Circuit Device Having Red... ...and 28 more

6/9/2008	Townsend And Townsend And Crew LLP	Assignee	Application Patent	08890584 5936905	Self Adjusting Delay Circuit And Method For Compensating Sense Amplifier... Self Adjusting Delay Circuit And Method For Compensating Sense Amplifier...

6/9/2008	Townsend And Townsend And Crew LLP	Assignee	Application Patent	08630283 5687108	Power Bussing Layout For Memory Circuits Power Bussing Layout For Memory Circuits

6/9/2008	Townsend And Townsend And Crew LLP	Assignee	Application Patent	08630310 5737267	Word Line Driver Circuit Word Line Driver Circuit

6/9/2008	Integrated Device Technology, Inc.	Assignee	Application Patent	09199884 6134176	Disabling A Defective Element In An Integrated Circuit Device Having Red... Disabling A Defective Element In An Integrated Circuit Device Having Red...

6/9/2008	Integrated Device Technology, Inc.	Assignee	Application Patent	09287948 6115302	Disabling A Decoder For A Defective Element In An Integrated Circuit Dev... Disabling A Decoder For A Defective Element In An Integrated Circuit Dev...

6/9/2008	Integrated Device Technology, Inc.	Assignee	Application Patent	09499265 6266264	Word line straps using two differentlayers of metal Word line straps using two differentlayers of metal

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09287948 6115302	Disabling A Decoder For A Defective Element In An Integrated Circuit Dev... Disabling A Decoder For A Defective Element In An Integrated Circuit Dev...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09199884 6134176	Disabling A Defective Element In An Integrated Circuit Device Having Red... Disabling A Defective Element In An Integrated Circuit Device Having Red...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09329975 6198682	Hierarchical Dynamic Memory Array Architecture Using Read Amplifiers Sep... Hierarchical Dynamic Memory Array Architecture Using Read Amplifiers Sep...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09502983 6240046	Integrated circuit random access memory capable of reading either one or... Integrated circuit random access memory capable of reading either one or...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09503109 6208575	Dynamic memory array bit line sense amplifier enabled to drive toward, b... Dynamic memory array bit line sense amplifier enabled to drive toward, b...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09503050 6373753	Memory array having selected word lines driven to an internally-generate... Memory array having selected word lines driven to an internally-generate...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09372320 6212109	Dynamic Memory Array Having Write Data Applied To Selected Bit Line Sens... Dynamic Memory Array Having Write Data Applied To Selected Bit Line Sens...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09451042 6104653	Equilibration Circuit And Method Using A Pulsed Equilibrate Signal And A... Equilibration Circuit And Method Using A Pulsed Equilibrate Signal And A...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09474351 6462998	Programmable And Electrically Configurable Latch Timing Circuit Programmable And Electrically Configurable Latch Timing Circuit

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09503108 6462584	Generating A Tail Current For A Differential Transistor Pair Using A Cap... Generating A Tail Current For A Differential Transistor Pair Using A Cap...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09503049 6282135	Intializing memory cells within a dynamic memory array prior to performi... Intializing memory cells within a dynamic memory array prior to performi...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09503048 6356485	Merging write cycles by comparing at least a portion of the respective w... Merging write cycles by comparing at least a portion of the respective w...

6/9/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09499265 6266264	Word line straps using two differentlayers of metal Word line straps using two differentlayers of metal

5/13/2008	Integrated Device Technology, Inc.	Assignor	Application Patent	09285232 6163475	Bit Line Cross-over Layout Arrangement Bit Line Cross-over Layout Arrangement

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09329975 6198682	Hierarchical Dynamic Memory Array Architecture Using Read Amplifiers Sep... Hierarchical Dynamic Memory Array Architecture Using Read Amplifiers Sep...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09372320 6212109	Dynamic Memory Array Having Write Data Applied To Selected Bit Line Sens... Dynamic Memory Array Having Write Data Applied To Selected Bit Line Sens...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09503050 6373753	Memory array having selected word lines driven to an internally-generate... Memory array having selected word lines driven to an internally-generate...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09503109 6208575	Dynamic memory array bit line sense amplifier enabled to drive toward, b... Dynamic memory array bit line sense amplifier enabled to drive toward, b...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09502983 6240046	Integrated circuit random access memory capable of reading either one or... Integrated circuit random access memory capable of reading either one or...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09499265 6266264	Word line straps using two differentlayers of metal Word line straps using two differentlayers of metal

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09503048 6356485	Merging write cycles by comparing at least a portion of the respective w... Merging write cycles by comparing at least a portion of the respective w...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09503049 6282135	Intializing memory cells within a dynamic memory array prior to performi... Intializing memory cells within a dynamic memory array prior to performi...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09474351 6462998	Programmable And Electrically Configurable Latch Timing Circuit Programmable And Electrically Configurable Latch Timing Circuit

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09451042 6104653	Equilibration Circuit And Method Using A Pulsed Equilibrate Signal And A... Equilibration Circuit And Method Using A Pulsed Equilibrate Signal And A...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09199884 6134176	Disabling A Defective Element In An Integrated Circuit Device Having Red... Disabling A Defective Element In An Integrated Circuit Device Having Red...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09287948 6115302	Disabling A Decoder For A Defective Element In An Integrated Circuit Dev... Disabling A Decoder For A Defective Element In An Integrated Circuit Dev...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09999563 6871261	Integrated Circuit Random Access Memory Capable Of Automatic Internal Re... Integrated Circuit Random Access Memory Capable Of Automatic Internal Re...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09503108 6462584	Generating A Tail Current For A Differential Transistor Pair Using A Cap... Generating A Tail Current For A Differential Transistor Pair Using A Cap...

12/9/2005	Integrated Device Technology, Inc.	Assignor	Application Patent	09285232 6163475	Bit Line Cross-over Layout Arrangement Bit Line Cross-over Layout Arrangement

3/24/2005	Integrated Device Technology, Inc.	Assignee	Application Publication Patent	10921760 20050152199 7016211	Dram-based Cam Cell With Shared Bitlines Dram-based Cam Cell With Shared Bitlines Dram-based Cam Cell With Shared Bitlines

1/27/2005	Sun Microsystems, Inc.	Assignee	Application Patent	11045940 7085178	Low-power Memory Write Circuits Low-power Memory Write Circuits

10/22/2004	Sun Microsystems, Inc.	Assignee	Application Publication Patent	10973114 20060087332 7106079	Using An Interposer To Facilate Capacitive Communication Between Face-to... Using An Interposer To Facilate Capacitive Communication Between Face-to... Using An Interposer To Facilate Capacitive Communication Between Face-to...

4/7/2004	Sun Microsystems, Inc.	Assignee	Application Patent	10820662 7148074	Method And Apparatus For Using A Capacitor Array To Measure Alignment Be... Method And Apparatus For Using A Capacitor Array To Measure Alignment Be...

3/26/2004	Sun Microsystems, Inc.	Assignee	Application Publication Patent	10810284 20050216876 7139993	Method And Apparatus For Routing Differential Signals Across A Semicondu... Method And Apparatus For Routing Differential Signals Across A Semicondu... Method And Apparatus For Routing Differential Signals Across A Semicondu...

12/17/2003	Integrated Device Technology, Inc.	Assignee	Application Patent	10643208 6856558	Integrated Circuit Devices Having High Precision Digital Delay Lines The... Integrated Circuit Devices Having High Precision Digital Delay Lines The...

10/2/2003	Integrated Device Technology, Inc.	Assignee	Application Patent	10410569 6804134	Content Addressable Memory (cam) Devices Having Cam Array Blocks Therein... Content Addressable Memory (cam) Devices Having Cam Array Blocks Therein...

10/2/2003	Integrated Device Technology, Inc.	Assignee	Application Patent	10386400 6839256	Content Addressable Memory (cam) Devices Having Dedicated Mask Cell Sub-... Content Addressable Memory (cam) Devices Having Dedicated Mask Cell Sub-...

10/2/2003	Integrated Device Technology, Inc.	Assignee	Application Patent	10613542 7669005	Content Addressable Memory (cam) Devices Having Soft Priority Resolution... Content Addressable Memory (cam) Devices Having Soft Priority Resolution...

8/7/2003	Townsend And Townsend And Crew LLP	Assignor	Application Patent	09516399 6323722	Apparatus For Translating A Voltage Apparatus For Translating A Voltage

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