Tessera, Inc.

From Wikipedia Individual tile used in a mosaic A tessera is an individual tile, usually formed in the shape of a square, used in creating a mosaic. It is also known as an abaciscus or abaculus. Read more on Wikipedia →

Federal Dockets	83
State Dockets	9
Active	1969–2017
Patent Assignments	1,998
Trademark Assignments	3,684
SEC Filings	4
SEC CIK	914573
Domicile	DE

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Document Type	Academic Paper Corporate Document - Internal Corporate Document - Public Court Document Equity Research Government Document - Federal Government Document - State Government Document - Local FBI File Public Records Request Response - FOIA Public Records Request Response - State Non-Profit Report Police Report White Paper
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Inside Counsel (7)

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Outside Counsel (258)

	Last Name	First Name	Middle Name	Firm	Location
				Goodwin Procter, LLP	Washington, DC
				Goodwin Procter, LLP	Menlo Park, CA
				Goodwin Procter, LLP	Washington, DC
				Goodwin Procter, LLP	Boston, MA
				Irell & Manella, LLP	Los Angeles, CA
				Finnegan, Henderson, Farabow, Garrett & Dunn...	Atlanta, GA
				Irell & Manella, LLP	Newport Beach, CA
				Gibson Dunn & Crutcher, LLP	San Francisco, CA
				Katherine K. Huang
				Michael B. Smith
				Sean Christopher Grimsley
				Gregory P. Stone
				Munger, Tolles & Olson LLP	Los Angeles, CA
				Munger, Tolles & Olson LLP	Los Angeles, CA
				Lupkin PLLC
				Kirkland & Ellis LLP	San Francisco, CA
				Capshaw DeRieux, LLP	Gladewater, TX
				Brian D. Ledahl
				Joseph M. Lipner
				Lisa N. Partain
				LIZA M. WALSH
				Melissa R. McCormick
				Philip A. Rovner
				Morgan Chu
				Gibson Dunn & Crutcher, LLP	Dallas, TX
				Dentons (US) LLP	Dallas, TX
				Devon Mobley-Ritter
				Robert T. Haslam
				Dale A. Rice
				Laura E. Muschamp
				Thomas Garten
				Anupam Sharma
				Kathryn Garcin
				Marianna F. Jackson
				Covington & Burling, LLP	Redwood Shores, CA
					Westfield, NJ
					San Jose, CA
					San Jose, CA
					SAN JOSE, CA
				Lerner David Littenberg Krumholz & Mentilk, ...	Westfield, NJ
					Seattle, WA
		Paul	H.	Lerner David Littenberg Krumholz & Mentilk, ...	Westfield, NJ
		TESSER		Hickman Palermo Truong & Becker, LLP	SAN JOSE, CA
	Addy	Sundeep	K.	Bartlit Beck LLP	Denver, CO
	Albert	Jennifer	A.	Hunton & Williams LLP	Washington, DC
	Arnold	A.	Joy	Ropes & Gray LLP	New York, NY
	Arvelo	Jose		Covington & Burling, LLP	Washington, DC
	Astin	Daniel	Kevin	Ciardi, Ciardi & Astin, PC	Wilmington, DE
	Aull	L.	Ashley	United States Department of Justice	Los Angeles, CA
	Barsky	Wayne	M.	Gibson Dunn & Crutcher, LLP	Los Angeles, CA
	Bartlit	Fred	H.	Bartlit Beck LLP	Chicago, IL
	Bass	Kenneth	Carrington	Sterne Kessler Goldstein & Fox, PLLC
	Beff	Daryl	K.	Lerner David Littenberg Krumholz & Mentilk, ...	WESTFIELD, NJ
	Bergeron	Ryan	L.
	Bessenger	F.	Leslie	Finnegan, Henderson, Farabow, Garrett & Dunn...	Mcdonough, GA
	Bishop	Gregory	S.	Pepper Hamilton, LLP	Redwood City, CA
	Blavin	Jonathan	H.	Munger, Tolles & Olson LLP
	Botos	Richard	J.	DOCKET ADMINISTRATOR AGERE SYSTEMS INC.	NEW JERSEY, NJ
	Bower	R		Finnegan, Henderson, Farabow, Garrett & Dunn...
	Brenza	Lindley		Bartlit Beck LLP	Chicago, IL
	Briers	Zachary	Michael	Munger, Tolles & Olson LLP	Los Angeles, CA
	Brown	Frederick		Gibson Dunn & Crutcher, LLP	San Francisco, CA
	Brown	Stephen		Maquet Cardiovascular LLC	WESTFIELD, NJ
	Caditz	Cindy		Davis Wright Tremaine LLP	Seattle, WA
	Canavan	Robert		Carlson, Gaskey & Olds, PC
	Capati	April		Cima 27, S.l.	WESTFIELD, NJ
	Capati	Arpil	M.	Lerner David Littenberg Krumholz & Mentilk, ...
	Capshaw	S	Calvin	Capshaw DeRieux, LLP
	Capshaw	Sidney	Calvin	Capshaw DeRieux, LLP	Longview, TX
	Carroll	Otis	W.	Ireland Carroll & Kelley	Tyler, TX
	Cave	Nicole	Teitler	Zagorin, O'brien &.	Austin, TX
	Chang	Jaemin		Fox Rothschild LLP	San Francisco, CA
	Chiu	Eric	K.	Munger, Tolles & Olson LLP
	Choa	Jonathan	A.	Jonathan A. Choa
	Choa	Jonathan	A.	Potter Anderson & Corroon LLP	Wilmington, DE
	Chu	Morgan		Irell & Manella, LLP	Los Angeles, CA
	Cole	Aaron	Hunter	Irell & Manella, LLP	Los Angeles, CA
	Craig	Amy	E.	Ramsey & Ehrlich LLP	Berkeley, CA
	Dane	Edward	George	Edward George Dane
	Dane	Ted	G.	Munger, Tolles & Olson LLP	Los Angeles, CA
	DeRieux	Elizabeth		Capshaw DeRieux, LLP	Longview, TX
	DOCKETING	PATENT		Covingon & Burling Llp	Washington, DC
	DOHERTY	MICHAEL	JOSEPH	dohertyiplaw.com Law Firm Placeholder	Washington, NJ
	DORIUS	KIRK		Zagorin O'Brien Graham LLP	AUSTIN, TX
	Downs	J.	Anthony	Goodwin Procter, LLP	Ma,
	Driscoll	Adrian	G.	Murphy Pearson Bradley & Feeney, PC	San Francisco, CA
	Ehrlich	Miles	F.	Ramsey & Ehrlich LLP	Berkeley, CA
	Eisner	Sara	L.	Wilson Sonsini Goodrich & Rosati, PC
	Eppich	Christopher	K.	Covington & Burling, LLP	San Diego, CA
	Ervin	Bradley	K.	Covington & Burling, LLP	Washington, DC
	Estrada	Miguel	A.	Gibson Dunn & Crutcher, LLP	Washington, DC
	Evans	Laura	Elizabeth	Wilson Sonsini Goodrich & Rosati, PC	Los Angeles, CA
	Evans	Taylor	P.	Lerner David Littenberg Krumholz & Mentilk, ...	WESTFIELD, CT
	Falcone	Anthony	E.	Irell & Manella, LLP
	Farnan	Brian	E.	Farnan LLP	Wilmington, DE
	Farnan	Michael	J.	Farnan LLP	Wilmington, DE
	Flugger	Kimberly	V.	Lerner David Littenberg Krumholz & Mentilk, ...	WESTFIELD,
	Fridman	Lawrence	C.	Lerner David Littenberg Krumholz & Mentilk, ...	WESTFIELD, NJ
	Friedland	Dustin		Google, Inc.

258 Rows Total	Page 1 of 3 | Go To

Filter By Form All Records REGDEX RW S-1 S-1/A From To

	Date	Entity	Form Number	Description	Value
	11/21/2005		REGDEX
	8/21/2001		RW
	10/20/2000		S-1/A	Amendment to S-1 registration statement
	9/5/2000		S-1	Registration statement for initial public offerings

4 Rows Total

	Date Recorded	Party	Role	Document Type	Document No.	Invention Title
	7/9/2026	International Business Machines Corporat...	Assignor	Application	19733611	Fabrication Of Nano-sheet Transistors With Different Threshold Voltages
	7/9/2026	International Business Machines Corporat...	Assignor	Application	19733611	Fabrication Of Nano-sheet Transistors With Different Threshold Voltages
	7/2/2026	International Business Machines Corporat...	Assignor	Application Application	19725466 18234767	Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density
	7/2/2026	International Business Machines Corporat...	Assignor	Application Application	19725466 18234767	Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density
	7/2/2026	International Business Machines Corporat...	Assignor	Application Application	18234767 19725466	Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density
	7/2/2026	International Business Machines Corporat...	Assignor	Application Application	19725466 18234767	Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density
	12/4/2025	International Business Machines Corporat...	Assignor	Application Publication	19327228 20260013208
	12/4/2025	Tessera LLC	Assignee	Application Publication	19327228 20260013208	Selective Removal Of Semiconductor Fins Selective Removal Of Semiconductor Fins
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	11821540 14058955 12838974 11546899 14034265 13970028 11580750 12321210 11318846 11021627 12842651 14242279 13356752 12722799 13711091 11588438 11642616 11803006 12842669 13335022 12830690 12829709 14834803 14147984 13929291 11581888 13012949 ...and 275 more	Microelectronic Packages With Nanoparticle Joining Packaged Semiconductor Chips With Array Chip Assembly Including Package Element And Integrated Circuit Chip Stacked Microelectronic Packages Having At Least Two Stacked Microelectr... Substrate For A Flexible Microelectronic Assembly And A Method Of Fabric... Microelectronic Packages Having Cavities For Receiving Microelectric Ele... Layered Metal Structure For Interconnect Element Microelectronic Packages Having Cavities For Receiving Microelectronic E... Wafer level edge stacking Flip Chip Interconnection With Double Post Microelectronic Package Comprising Offset Conductive Posts On Compliant ... Off-chip Vias In Stacked Chips Wafer Level Chip Package And A Method Of Fabricating Thereof Microelectronic Packages And Methods Therefor Multi-sheet Conductive Substrates For Microelectronic Devices And Method... Microelectronic Packages And Methods Therefor Method Of Fabricating Stacked Assembly Including Plurality Of Stacked Mi... Interconnection Element With Posts Formed By Plating Multilayer Wiring Element Having Pin Interface Microelectronic Packages With Dual Or Multiple-etched Flip-chip Connecto... Stackable Molded Microelectronic Packages Enabling Uniformity Of Stacking Process Through Bumpers Compact Lens Turret Assembly Microelectronic Assembly With Impedance Controlled Wirebond And Referenc... Microelectronic Assembly With Impedance Controlled Wirebond And Conducti... Stackable Molded Microelectronic Packages Microelectronic Package Element And Method Of Fabricating Thereof ...and 275 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	12958866 14104407 13193814 13076969 13155552 13097943 15823210 15066238 13291297 13306182 13156609 13080876 13092376 14451136 13158797 13939725 14286159 13194754 14252197 14801259 14525462 13051424 12842692 13658401 14199181 12884695 14094621 ...and 275 more	Stacked Microelectronic Assembly With Tsvs Formed In Stages With Plural ... Deskewed Multi-die Packages Non-lithographic Formation Of Three-dimensional Conductive Elements Stacked Chip-on-board Module With Edge Connector Staged via formation from both sides of chip Stacked Microelectronic Assembly With Tsvs Formed In Stages And Carrier ... Void-free Wafer Bonding Using Channels Staged Via Formation From Both Sides Of Chip Interconnect Structure Staged Via Formation From Both Sides Of Chip Low Stress Vias Multi-chip Module With Stacked Face-down Connected Dies Dram Security Erase Active Chip On Carrier Or Laminated Chip Having Microelectronic Element ... Enhanced Stacked Microelectronic Assemblies With Central Contacts And Vi... Multi-function And Shielded 3d Interconnects Multi-Function and Shielded 3D Interconnects Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Stacked Microelectronic Assembly With Tsvs Formed In Stages With Plural ... Microelectronic Elements With Post-assembly Planarization Power Boosting Circuit For Semiconductor Packaging Systems and Methods for Producing Flat Surfaces in Interconnect Structur... Multiple Die Stacking For Two Or More Die Chip Assembly Having Via Interconnects Joined By Plating Active Chip On Carrier Or Laminated Chip Having Microelectronic Element ... Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Stacked Microelectronic Assemby With Tsvs Formed In Stages And Carrier A... ...and 275 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 260 more	12835306 15195641 15391393 15650530 15198992 15405344 14510606 14559962 14154206 15797315 13422606 14589222 15450508 14526741 15046055 14883882 15210991 16440106 13716636 15816508 14883913 15808193 14708885 15834354 15798794 15244499 15480750 ...and 260 more	Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Reliable Packaging And Interconnect Structures Dual Work Function Integration For Stacked Finfet Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Low Resistance And Inductance Backside Through Vias And Methods Of Fabri... Method And Apparatus For Forming Nickel Silicide With Low Defect Density... Insulating A Via In A Semiconductor Substrate Reliable Packaging And Interconnect Structures Interconnect Structure Having Subtractive Etch Feature And Damascene Fea... Stack Packages Using Reconstituted Wafers Method To Form Stacked Germanium Nanowires And Stacked Iii-v Nanowires Semiconductor Fins For Finfet Devices And Sidewall Image Transfer (sit) ... Optimized Wires For Resistance Or Electromigration Stress Retention In Fins Of Fin Field-effect Transistors Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Performance Optimized Gate Structures Method Of Forming A Three-dimensional Bonded Semiconductor Structure Hav... Reduction Of Stress In Via Structure Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage High-k/metal Gate Mosfet With Reduced Parasitic Capacitance Stress Retention In Fins Of Fin Field-effect Transistors Integration Of Super Via Structure In Beol Heterogeneous Source Drain Region And Extension Region Integration Of Super Via Structure In Beol Increasing Electromigration Lifetime And Current Densityin Ic Using Vert... ...and 260 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 263 more	14699716 14805669 15189579 14643011 14749770 15664811 15671847 14846801 15182726 14187896 14944355 14672350 13089958 15361794 15157891 15359929 15634307 14197959 15982558 14924162 15613774 15136048 14960483 14301587 14139121 15583310 14948745 ...and 263 more	Finfet Device With Vertical Silicide On Recessed Source/drain Epitaxy Re... Self-aligned Contact Process Enabled By Low Temperature Iii-v Semiconductor Devices With Selective Oxidation Sidewall Image Transfer Nanosheet Replacement Metal Gate Dielectric Cap Low Resistance Metal Contacts To Interconnects Method For Manufacturing Interconnect Structures Incorporating Air Gap S... Fin Pitch Scaling For High Voltage Devices And Low Voltage Devices On Th... Stacked Semiconductor Nanowires With Tunnel Spacers Homogeneous Densification Of Fill Layers For Controlled Reveal Of Vertic... Air Gap Structure With Bilayer Selective Cap Trenched Gate With Sidewall Airgap Spacer Spin Transfer Torque Cell For Magnetic Random Access Memory BULK SILICON GERMANIUM FinFET Microstructure Modification In Copper Interconnect Structure Nanosheet Mosfet With Full-height Air-gap Spacer Low Resistance Contact Structures For Trench Structures Overlap Capacitance Nanowire Finfet Device With Vertical Silicide On Recessed Source/drain Epitaxy Re... Fin Pitch Scaling For High Voltage Devices And Low Voltage Devices On Th... FIN FIELD-EFFECT TRANSISTOR (FinFET) WITH REDUCED PARASITIC CAPACITANCE Multi-layer Work Function Metal Replacement Gate Low Resistance Contact Structures Including A Copper Fill For Trench Str... Method For Manufacturing Interconnect Structures Incorporating Air Gap S... Semiconductor Device Including Merged-unmerged Work Function Metal And V... Low Resistance Contact Structures For Trench Structures Fin Density Control Of Multigate Devices Through Sidewall Image Transfer... ...and 263 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 187 more	15462501 15260509 15445107 15629306 15331331 15177917 15276985 15403667 15591278 16276118 16028495 16238193 15431807 15251775 15801933 15430764 15819577 15678328 15241898 15140763 15628821 15207802 15701894 16250351 15465962 15918870 15339283 ...and 187 more	Efficient Metal-insulator-metal Capacitor Fabrication Forming Gates With Varying Length Using Sidewall Image Transfer Fin Cut During Replacement Gate Formation Nanosheet Transistors On Bulk Material Cobalt Contact And Interconnect Structures Low Aspect Ratio Interconnect Vertical Field Effect Transistors With Metallic Source/drain Regions Preserving Channel Strain In Fin Cuts Method And Structure For Cut Material Selection Stacked Complementary Fets Featuring Vertically Stacked Horizontal Nanow... Uniform Fin Dimensions Using Fin Cut Hardmask Nanosheet Transistors On Bulk Material Fin Cut During Replacement Gate Formation Forming Insulator Fin Structure In Isolation Region To Support Gate Stru... Forming A Hybrid Channel Nanosheet Semiconductor Structure Reduced Resistance Source And Drain Extensions In Vertical Field Effect ... Semiconductor Device With Different Fin Pitches Transistor With Improved Air Spacer Efficient Metal-insulator-metal Capacitor Margin For Fin Cut Using Self-aligned Triple Patterning Reduced Resistance Source And Drain Extensions In Vertical Field Effect ... Self-aligned Air Gap Spacer For Nanosheet Cmos Devices Cobalt Contact And Interconnect Structures Forming A Contact For A Semiconductor Device Margin For Fin Cut Using Self-aligned Triple Patterning Transistor With Air Spacer And Self-aligned Contact Alternating Hardmasks For Tight-pitch Line Formation ...and 187 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	13156609 12883431 13306182 13194669 12883421 13157722 14219398 14046233 14058908 14286159 14162011 12965192 13080876 13155719 13168675 12884649 14501915 13195187 14270885 14525462 14181466 14499162 14497572 13940582 12953994 13158797 13194754 ...and 275 more	Laminated Chip Having Microelectronic Element Embedded Therein Three-dimensional System-in-a-package Low Cost Hybrid High Density Package Microelectronic Elements With Post-assembly Planarization Multi-chip Module With Stacked Face-down Connected Dies Dram Security Erase Staged via formation from both sides of chip Multiple Die Face-down Stacking For Two Or More Die Single Exposure In Multi-damascene Process Multi-function And Shielded 3d Interconnects Stacked Chip-on-board Module With Edge Connector Embedded Passive Integration Flow Underfill For Microelectronic Packages Flip Chip Assembly And Process With Sintering Material On Metal Bumps Enhanced Stacked Microelectronic Assemblies With Central Contacts And Vi... Substrate And Assembly Thereof With Dielectric Removal For Increased Pos... Void-free Wafer Bonding Using Channels Through Interposer Wire Bond Using Low Cte Interposer With Coarse Slot A... Active Chip On Carrier Or Laminated Chip Having Microelectronic Element ... Dual Wafer Spin Coating Microelectronic Package With Stacked Microelectronic Elements And Method... Microelectronic Elements With Post-assembly Planarization Pin Attachment Dram Security Erase Staged Via Formation From Both Sides Of Chip Multiple Die Face-down Stacking For Two Or More Die Single Exposure In Multi-damascene Process ...and 275 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	13741890 14642588 14094621 12958866 13215725 15066238 15047295 14689346 15082951 15131966 12970529 13155845 12884695 13287237 15823210 13076969 14513563 14104407 13091800 14245773 12842587 13939725 13193814 14340159 14221486 13195786 13618514 ...and 275 more	Stacked Microelectronic Assembly With Tsvs Formed In Stages And Carrier ... Multiple Die Stacking For Two Or More Die System And Method For Testing Fuse Blow Reliability For Integrated Circu... Conductive Pads Defined By Embedded Traces Flip-chip, Face-up And Face-down Wirebond Combination Package Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Enhanced Stacked Microelectronic Assemblies With Central Contacts And Im... Semiconductor Chip Package Assembly And Method For Making Same Stacked Microelectronic Assembly With Tsvs Formed In Stages With Plural ... Low-stress Vias Active Chip On Carrier Or Laminated Chip Having Microelectronic Element ... Compliant Interconnects In Wafers Low-stress Tsv Design Using Conductive Particles Microelectronic Elements With Post-assembly Planarization Interconnect Structure Dram Security Erase Chip Assembly Having Via Interconnects Joined By Plating Multiple Die Face-down Stacking For Two Or More Die Packaged Microelectronic Elements Having Blind Vias For Heat Dissipation Stacked Microelectronic Assemby With Tsvs Formed In Stages And Carrier A... Interposer Having Molded Low Cte Dielectric System And Method For Testing Fuse Blow Reliability For Integrated Circu... Multi-Function and Shielded 3D Interconnects Flip-chip, Face-up And Face-down Wirebond Combination Package Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Stacked Chip Assembly Having Vertical Vias Deskewed Multi-die Packages ...and 275 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 260 more	15480750 15623228 15244499 14559962 16983764 15850446 12671993 15795445 14154206 14561514 13422606 15650530 12410728 15166570 14553521 14883882 15260675 15199129 12634726 15075944 15046559 15149326 14883913 15260679 15727956 12835306 15075960 ...and 260 more	Increasing Electromigration Lifetime And Current Densityin Ic Using Vert... Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Integration Of Thick And Thin Nanosheet Transistors On A Single Chip Graphene And Metal Interconnects Method Of Forming Performance Optimized Gate Structures By Silicidizing ... Fin End Spacer For Preventing Merger Of Raised Active Regions Dual Work Function Integration For Stacked Finfet Method And Structure For Robust Finfet Replacement Metal Gate Integratio... Structure And Fabrication Method For Electromigration Immortal Nanoscale... Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Heterogeneous Source Drain Region And Extension Region Improving Channel Strain And Controlling Lateral Epitaxial Growth Of The... Reliable Packaging And Interconnect Structures Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Interconnect Structure Having Subtractive Etch Feature And Damascene Fea... Integrated Structures Of High Performance Active Devices And Passive Dev... Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage WET ETCH REMOVAL OF Ru SELECTIVE TO OTHER METALS Copper Wire And Dielectric With Air Gaps Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Integration Of Super Via Structure In Beol Integrated Decoupling Capacitor Employing Conductive Through-substrate V... Optimized Wires For Resistance Or Electromigration Fin End Spacer For Preventing Merger Of Raised Active Regions Dual Work Function Integration For Stacked Finfet Dielectric Liner For A Self-aligned Contact Via Structure Semiconductor Fins For Finfet Devices And Sidewall Image Transfer (sit) ... ...and 260 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 260 more	15650530 12410728 15166570 14553521 14883882 15260675 13422606 15199129 12634726 15075944 15046559 15149326 14883913 15260679 15727956 12835306 15075960 15149360 14884045 14561550 13426835 15076012 14721430 14739008 15179699 15070154 15824537 ...and 260 more	Copper Wire And Dielectric With Air Gaps Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Reduction Of Stress In Via Structure Method And Apparatus For Forming Nickel Silicide With Low Defect Density... Optimized Wires For Resistance Or Electromigration Fin End Spacer For Preventing Merger Of Raised Active Regions Method Of Forming Performance Optimized Gate Structures By Silicidizing ... Sti Region For Small Fin Pitch In Finfet Devices Semiconductor Fins For Finfet Devices And Sidewall Image Transfer (sit) ... Finfet With Constrained Source-drain Epitaxial Region Insulating A Via In A Semiconductor Substrate Electrical Barrier Layers Heterogeneous Source Drain Region And Extension Region Stress Retention In Fins Of Fin Field-effect Transistors Stack Packages Using Reconstituted Wafers Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Method Of Forming A Three-dimensional Bonded Semiconductor Structure Hav... Reduction Of Stress In Via Structure Method And Apparatus For Forming Nickel Silicide With Low Defect Density... Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Homogeneous Densification Of Fill Layers For Controlled Reveal Of Vertic... Graphene And Metal Interconnects With Reduced Contact Resistance Performance Optimized Gate Structures Fin End Spacer For Preventing Merger Of Raised Active Regions Semiconductor Fins For Finfet Devices And Sidewall Image Transfer (sit) ... Finfet With Constrained Source-drain Epitaxial Region Sidewall Image Transfer Process For Fin Patterning ...and 260 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 263 more	14805669 15593933 14748424 14536751 15345595 16103085 15361794 14944355 16505063 15634307 14225812 16853161 14613667 13083550 15680697 14175441 15063735 14643011 13089958 14919201 14953908 15294376 15289467 14846800 15226143 14583454 14962082 ...and 263 more	Finfet Device With Vertical Silicide On Recessed Source/drain Epitaxy Re... Fin Pitch Scaling For High Voltage Devices And Low Voltage Devices On Th... Self-aligned Contact Process Enabled By Low Temperature Low Resistance Contact Structures For Trench Structures Method For Manufacturing Interconnect Structures Incorporating Air Gap S... Iii-v Semiconductor Devices With Selective Oxidation Finfet Device Formed By A Replacement Metal-gate Method Including A Gate... Spin Transfer Torque Cell For Magnetic Random Access Memory Stable Multiple Threshold Voltage Devices On Replacement Metal Gate Cmos... Nanosheet Mosfet With Full-height Air-gap Spacer Multi-layer Work Function Metal Replacement Gate Air Gap Contact Formation For Reducing Parasitic Capacitance Sidewall Image Transfer Nanosheet Lowering Parasitic Capacitance Of Replacement Metal Gate Processes Hybrid Subtractive Etch/metal Fill Process For Fabricating Interconnects Fin Type Field Effect Transistors With Different Pitches And Substantial... Silicon Nanowire Formation In Replacement Metal Gate Process Asymmetric Finfet Memory Access Transistor Gate Structure Integration Scheme For Fin Field Effect Transistors Methods For Removal Of Selected Nanowires In Stacked Gate All Around Arc... Self-aligned Contact Process Enabled By Low Temperature Low Resistance Contact Structures For Trench Structures Interconnect Structures Incorporating Air-gap Spacers Iii-v Semiconductor Devices With Selective Oxidation Bulk Fin Sti Formation Spin Transfer Torque Cell For Magnetic Random Access Memory Fin Cut On Sit Level ...and 263 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 263 more	15583310 14940685 14501654 13168477 14869066 15075260 15430667 14197959 14699716 14858628 15417940 15487685 15430672 14984194 14959046 15088849 14951593 16032213 15982558 14749811 14028053 15671847 14975725 14551322 14924162 15015347 14949386 ...and 263 more	Overlap Capacitance Nanowire Hybrid Subtractive Etch/metal Fill Process For Fabricating Interconnects Sidewall Image Transfer Nanosheet Fin Density Control Of Multigate Devices Through Sidewall Image Transfer... Perpendicular Magnetic Anisotropy Free Layers With Iron Insertion And Ox... Semiconductor Device Including Merged-unmerged Work Function Metal And V... Fin Cut Without Residual Fin Defects Self-aligned Contact Process Enabled By Low Temperature Fin Pitch Scaling For High Voltage Devices And Low Voltage Devices On Th... Homogeneous Densification Of Fill Layers For Controlled Reveal Of Vertic... Replacement Metal Gate Dielectric Cap Low Resistance Contact Structures For Trench Structures Microstructure Modification In Copper Interconnect Structure Air Gap Structure With Bilayer Selective Cap Hybrid Airgap Structure With Oxide Liner Spin Transfer Torque Cell For Magnetic Random Access Memory Stable Multiple Threshold Voltage Devices On Replacement Metal Gate Cmos... Fin Field-effect Transistor (finfet) With Reduced Parasitic Capacitance Overlap Capacitance Nanowire Hybrid Subtractive Etch/metal Fill Process For Fabricating Interconnects Sidewall Image Transfer Nanosheet Very Planar Gate Cut Post Replacement Gate Process Low Resistance Metal Contacts To Interconnects Stacked Nanowire Devices Silicon Nanowire Formation In Replacement Metal Gate Process Fin Cut Without Residual Fin Defects Finfet Device With Vertical Silicide On Recessed Source/drain Epitaxy Re... ...and 263 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 187 more	15450725 15695319 15403667 15172598 15604090 15850891 15801933 15339283 15431807 15465989 16276118 15404469 15177917 15790826 15811812 15462501 15676263 15443451 15331331 15294906 16023687 15805829 15258378 15620095 15617001 15680711 16038600 ...and 187 more	Semiconductor Device With Different Fin Pitches Transistor With Air Spacer And Self-aligned Contact Multi-layer Filled Gate Cut To Prevent Power Rail Shorting To Gate Struc... Nanosheet Transistors Having Different Gate Dielectric Thicknesses On Th... Uniform Fin Dimensions Using Fin Cut Hardmask Efficient Metal-insulator-metal Capacitor Fabrication Forming A Hybrid Channel Nanosheet Semiconductor Structure Nanosheet Transistors On Bulk Material Integrating And Isolating Nfet And Pfet Nanosheet Transistors On A Subst... Preserving Channel Strain In Fin Cuts Forming A Contact For A Semiconductor Device Forming Insulator Fin Structure In Isolation Region To Support Gate Stru... Multiple Finfet Formation With Epitaxy Separation Forming Gates With Varying Length Using Sidewall Image Transfer Transistor With Air Spacer And Self-aligned Contact Multi-layer Filled Gate Cut To Prevent Power Rail Shorting To Gate Struc... Nanosheet Transistors Having Different Gate Dielectric Thicknesses On Th... Structure And Method For Improved Stabilization Of Cobalt Cap And/or Cob... Efficient Metal-insulator-metal Capacitor Forming A Hybrid Channel Nanosheet Semiconductor Structure Nanosheet Transistors On Bulk Material Integrating And Isolating Nfet And Pfet Nanosheet Transistors On A Subst... Self-aligned Air Gap Spacer For Nanosheet Cmos Devices Approach To Minimization Of Strain Loss In Strained Fin Field Effect Tra... Forming Insulator Fin Structure In Isolation Region To Support Gate Stru... Inner Spacer For Nanosheet Transistors Forming Gates With Varying Length Using Sidewall Image Transfer ...and 187 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 187 more	16052161 16238193 15263959 15617001 15680711 16038600 15336886 16871935 15260509 15697539 15285728 15134497 15819577 16798823 15186600 15591278 15467690 15459684 15430764 15690601 15846447 15276985 15851095 15826841 16019916 15846461 15142450 ...and 187 more	Forming A Hybrid Channel Nanosheet Semiconductor Structure Nanosheet Transistors On Bulk Material Integrating And Isolating Nfet And Pfet Nanosheet Transistors On A Subst... Preserving Channel Strain In Fin Cuts Forming A Contact For A Semiconductor Device Forming Insulator Fin Structure In Isolation Region To Support Gate Stru... Stacked Complementary Fets Featuring Vertically Stacked Horizontal Nanow... Semiconductor Device With Different Fin Pitches Transistor With Air Spacer And Self-aligned Contact Multi-layer Filled Gate Cut To Prevent Power Rail Shorting To Gate Struc... Nanosheet Transistors Having Different Gate Dielectric Thicknesses On Th... Uniform Fin Dimensions Using Fin Cut Hardmask Efficient Metal-insulator-metal Capacitor Fabrication Margin For Fin Cut Using Self-aligned Triple Patterning Self-aligned Air Gap Spacer For Nanosheet Cmos Devices Approach To Minimization Of Strain Loss In Strained Fin Field Effect Tra... Forming Insulator Fin Structure In Isolation Region To Support Gate Stru... Inner Spacer For Nanosheet Transistors Forming Gates With Varying Length Using Sidewall Image Transfer Transistor With Air Spacer And Self-aligned Contact Copper Interconnect Structures Nanosheet Transistors Having Different Gate Dielectric Thicknesses On Th... Structure And Method For Improved Stabilization Of Cobalt Cap And/or Cob... Efficient Metal-insulator-metal Capacitor Forming A Hybrid Channel Nanosheet Semiconductor Structure Nanosheet Transistors On Bulk Material Margin For Fin Cut Using Self-aligned Triple Patterning ...and 187 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	13929291 11642616 13407085 13711091 11318846 11973869 12965172 11318822 14177527 14058955 11506472 11801336 15282255 12004149 14753895 14707465 11581888 11645016 12722784 12321210 11318164 11809213 12842717 11546899 11704713 10985126 11648719 ...and 275 more	Stacked Microelectronic Packages Having At Least Two Stacked Microelectr... Wafer Level Chip Package And A Method Of Fabricating Thereof Microelectronic Assembly With Impedance Controlled Wirebond And Referenc... Multi-sheet Conductive Substrates For Microelectronic Devices And Method... Edge Connect Wafer Level Stacking Tsop With Impedance Control Microelectronic Connection Component Method Of Fabricating Stacked Packages With Bridging Traces Microelectronic Packages With Dual Or Multiple-etched Flip-chip Connecto... Microelectronic Packages And Methods Therefor Packaged Semiconductor Chips With Array Microelectronic Elements With Rear Contacts Connected With Via First Or ... Image Sensor Employing A Plurality Of Photodetector Arrays And/or Rear-i... Microelectronic Assemblies Having Compliancy And Methods Therefor Microelectronic Package With Thermal Access Wearable Ultra-thin Miniaturized Mobile Communications Microelectronic Package Comprising Offset Conductive Posts On Compliant ... Substrate For A Microelectronic Package And Method Of Fabricating Thereo... A Method Of Fabricating An Interconnection Element Having Conductive Pos... Stacked Packaging Improvements Edge connect wafer level stacking Wafer Level Edge Stacking Microelectronic Component With Foam-metal Posts Stacked packages with bridging traces Stackable Molded Microelectronic Packages Microelectronic Packages Fabricated At The Wafer Level And Methods There... Packaged Semiconductor Chips ...and 275 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	12953994 13158797 13194754 15174983 13092376 13216918 14243484 13051414 14829810 13168839 15842080 14461919 14628894 14686222 14060997 13950912 14199181 13051424 14623161 13291297 12842692 14811177 13155552 14814344 14224379 13306300 14199156 ...and 275 more	Microelectronic Package With Stacked Microelectronic Elements And Method... Microelectronic Elements With Post-assembly Planarization Pin Attachment Dram Security Erase Staged Via Formation From Both Sides Of Chip Multiple Die Face-down Stacking For Two Or More Die Packaged Microelectronic Elements Having Blind Vias For Heat Dissipation Stacked Microelectronic Assembly With Tsvs Formed In Stages And Carrier ... Stacked Chip-on-board Module With Edge Connector Reliable Wire Structure And Method Microelectronic Package With Terminals On Dielectric Mass A Method For Making A Microelectronic Package Includes Joining The Condu... Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Enhanced Stacked Microelectronic Assemblies With Central Contacts Interconnection Elements With Encased Interconnects Stacked Microelectronic Assembly Having Interposer Connecting Active Chi... Low-stress Vias Active Chip On Carrier Or Laminated Chip Having Microelectronic Element ... Compliant Interconnects In Wafers Carrier Structures For Microelectronic Elements Interconnect Structure Dram Security Erase Staged Via Formation From Both Sides Of Chip Multiple Die Face-down Stacking For Two Or More Die Packaged Microelectronic Elements Having Blind Vias For Heat Dissipation Stacked Microelectronic Assembly With Tsvs Formed In Stages And Carrier ... Multiple Die Stacking For Two Or More Die ...and 275 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	13950912 14199181 13051424 14623161 13291297 14686222 14060997 13155552 14814344 14224379 13306300 14199156 12842692 14811177 13215725 15066238 15047295 13741890 14642588 14094621 12958866 13155845 12884695 14689346 15082951 15131966 12970529 ...and 275 more	Non-lithographic Formation Of Three-dimensional Conductive Elements Simultaneous Wafer Bonding And Interconnect Joining Through Interposer Wire Bond Using Low Cte Interposer With Coarse Slot A... Active Chip On Carrier Or Laminated Chip Having Microelectronic Element ... Three-dimensional System-in-a-package Low Cost Hybrid High Density Package Microelectronic Elements With Post-assembly Planarization Multi-chip Module With Stacked Face-down Connected Dies Power Boosting Circuit For Semiconductor Packaging Staged Via Formation From Both Sides Of Chip Interposer Having Molded Low Cte Dielectric Single Exposure In Multi-damascene Process Multi-function And Shielded 3d Interconnects Stacked Chip-on-board Module With Edge Connector Systems and Methods for Producing Flat Surfaces in Interconnect Structur... Flow Underfill For Microelectronic Packages Flip Chip Assembly And Process With Sintering Material On Metal Bumps Stacked Microelectronic Assembly With Tsvs Formed In Stages With Plural ... Substrate And Assembly Thereof With Dielectric Removal For Increased Pos... Void-free Wafer Bonding Using Channels Low Stress Vias Active Chip On Carrier Or Laminated Chip Having Microelectronic Element ... Dual Wafer Spin Coating Low Cost Hybrid High Density Package Microelectronic Elements With Post-assembly Planarization Multi-chip Module With Stacked Face-down Connected Dies Dram Security Erase ...and 275 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 260 more	14559962 16983764 15480750 15623228 15244499 14154206 14561514 15850446 12671993 15795445 14883882 15260675 13422606 15650530 12410728 15166570 14553521 15149326 14883913 15260679 15727956 15199129 12634726 15075944 15046559 15149360 14884045 ...and 260 more	Structure And Fabrication Method For Electromigration Immortal Nanoscale... Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Heterogeneous Source Drain Region And Extension Region Improving Channel Strain And Controlling Lateral Epitaxial Growth Of The... Reliable Packaging And Interconnect Structures Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Interconnect Structure Having Subtractive Etch Feature And Damascene Fea... Integrated Structures Of High Performance Active Devices And Passive Dev... Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage WET ETCH REMOVAL OF Ru SELECTIVE TO OTHER METALS Increasing Electromigration Lifetime And Current Densityin Ic Using Vert... Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Integration Of Thick And Thin Nanosheet Transistors On A Single Chip Graphene And Metal Interconnects Method Of Forming Performance Optimized Gate Structures By Silicidizing ... Fin End Spacer For Preventing Merger Of Raised Active Regions Dual Work Function Integration For Stacked Finfet Method And Structure For Robust Finfet Replacement Metal Gate Integratio... Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Self-aligned Quadruple Patterning Process Channel Strain And Controlling Lateral Epitaxial Growth Of The Source An... Reliable Packaging And Interconnect Structures Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Interconnect Structure Having Substractive Etch Feature And Damascene Fe... Chip Guard Ring Including A Through-substrate Via Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage 3d Bonded Semiconductor Structure With An Embedded Resistor ...and 260 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 260 more	14330158 14754999 13716636 15815061 16440106 15808193 15195641 15244499 14559962 16983764 15480750 15623228 14154206 14561514 15850446 12671993 15795445 14883882 15260675 13422606 15650530 12410728 15166570 14553521 15046559 15149326 14883913 ...and 260 more	Reliable Packaging And Interconnect Structures Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Interconnect Structure Having Substractive Etch Feature And Damascene Fe... Chip Guard Ring Including A Through-substrate Via Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage 3d Bonded Semiconductor Structure With An Embedded Resistor Copper Wire And Dielectric With Air Gaps Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Integration Of Super Via Structure In Beol Integrated Decoupling Capacitor Employing Conductive Through-substrate V... Optimized Wires For Resistance Or Electromigration Fin End Spacer For Preventing Merger Of Raised Active Regions Dual Work Function Integration For Stacked Finfet Dielectric Liner For A Self-aligned Contact Via Structure Semiconductor Fins For Finfet Devices And Sidewall Image Transfer (sit) ... Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Self-aligned Quadruple Patterning Process Channel Strain And Controlling Lateral Epitaxial Growth Of The Source An... Reliable Packaging And Interconnect Structures Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Interconnect Structure Having Subtractive Etch Feature And Damascene Fea... Low Resistance And Inductance Backside Through Vias And Methods Of Fabri... Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage 3d Bonded Semiconductor Structure With An Embedded Capacitor Copper Wire And Dielectric With Air Gaps Asymmetric High-k Dielectric For Reducing Gate Induced Drain Leakage Hybrid Bonding Techniques For Multi-layer Semiconductor Stacks ...and 260 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	11317207 11603935 12832376 11025401 13356752 12228890 11642616 13407085 13711091 11318846 11973869 13929291 11318822 14177527 14058955 11506472 11801336 12965172 14753895 14707465 11581888 11645016 15282255 12004149 11809213 12842717 11546899 ...and 275 more	Microelectronic Assemblies Having Very Fine Pitch Stacking Wearable Ultra-thin Miniaturized Mobile Communications Method Of Making A Connection Component With Posts And Pads Substrate For A Microelectronic Package And Method Of Fabricating Thereo... Reconstituted Wafer Stack Packaging With After-applied Pad Extensions Microelectronic Package Having Stacked Semiconductor Devices And A Proce... Wafer Level Chip Package And A Method Of Fabricating Thereof Microelectronic Assembly With Impedance Controlled Wirebond And Conducti... Stacked Packaging Improvements Edge connect wafer level stacking Wafer Level Edge Stacking Microelectronic Component With Foam-metal Posts Stacked packages with bridging traces Stackable Molded Microelectronic Packages Microelectronic Packages Fabricated At The Wafer Level And Methods There... Packaged Semiconductor Chips Microelectronic Elements Having Metallic Pads Overlying Vias Microelectronic Package Having Interconnected Redistribution Paths Chip Assembly Including Package Element And Integrated Circuit Chip Pin Referenced Image Sensor To Reduce Tilt In A Camera Module Multilayer Wiring Element Having Pin Interface Microelectronic Package Element And Method Of Fabricating Thereof Off-chip Vias In Stacked Chips Image Sensor Package And Fabrication Method Ultra-thin near-hermetic package based on rainier Robust Multi-layer Wiring Elements And Assemblies With Embedded Microele... Stacked Packaging Improvements ...and 275 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	13158797 13194754 15174983 13092376 13216918 12953994 14829810 13168839 15842080 14461919 14628894 14243484 13051414 13950912 14199181 13051424 14623161 13291297 14686222 14060997 14814344 14224379 13306300 14199156 12842692 14811177 13155552 ...and 275 more	Enhanced Stacked Microelectronic Assemblies With Central Contacts Interconnection Elements With Encased Interconnects Stacked Microelectronic Assembly Having Interposer Connecting Active Chi... Low-stress Vias Active Chip On Carrier Or Laminated Chip Having Microelectronic Element ... Compliant Interconnects In Wafers Microelectronic Package With Stacked Microelectronic Elements And Method... Microelectronic Elements With Post-assembly Planarization Pin Attachment Dram Security Erase Staged Via Formation From Both Sides Of Chip Multiple Die Face-down Stacking For Two Or More Die Packaged Microelectronic Elements Having Blind Vias For Heat Dissipation Stacked Microelectronic Assembly With Tsvs Formed In Stages And Carrier ... Stacked Chip-on-board Module With Edge Connector Reliable Wire Structure And Method Microelectronic Package With Terminals On Dielectric Mass A Method For Making A Microelectronic Package Includes Joining The Condu... Systems And Methods For Producing Flat Surfaces In Interconnect Structur... Enhanced Stacked Microelectronic Assemblies With Central Contacts Semiconductor Chip Package Assembly And Method For Making Same Stacked Microelectronic Assembly With Tsvs Formed In Stages With Plural ... Low-stress Vias Active Chip On Carrier Or Laminated Chip Having Microelectronic Element ... Compliant Interconnects In Wafers Microelectronic Package With Stacked Microelectronic Elements And Method... Carrier Structures For Microelectronic Elements ...and 275 more
	11/21/2025	Tessera LLC	Assignee	Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application Application ...and 275 more	11821540 12221924 12769930 12148144 12838974 14529279 11825121 12143743 13012949 14034265 13926165 11642570 11606771 12941392 14242279 14814781 14559412 14011086 13914896 14933225 11604020 14834803 14574988 11803006 13911555 11809214 12857054 ...and 275 more	Stacked Microelectronic Packages Having At Least Two Stacked Microelectr... Wafer Level Chip Package And A Method Of Fabricating Thereof Microelectronic Assembly With Impedance Controlled Wirebond And Conducti... Stacked Packaging Improvements Edge Connect Wafer Level Stacking Tsop With Impedance Control Microelectronic Component With Foam-metal Posts Method Of Fabricating Stacked Packages With Bridging Traces Stackable Molded Microelectronic Packages Microelectronic Packages And Methods Therefor Packaged Semiconductor Chips Microelectronic Elements Having Metallic Pads Overlying Vias Microelectronic Package Having Interconnected Redistribution Paths Chip Assembly Including Package Element And Integrated Circuit Chip Microelectronic Assemblies Having Very Fine Pitch Stacking Wearable Ultra-thin Miniaturized Mobile Communications Method Of Making A Connection Component With Posts And Pads Substrate For A Microelectronic Package And Method Of Fabricating Thereo... Reconstituted Wafer Stack Packaging With After-applied Pad Extensions Microelectronic Package Having Stacked Semiconductor Devices And A Proce... Ultra-thin near-hermetic package based on rainier Robust Multi-layer Wiring Elements And Assemblies With Embedded Microele... Stacked Packaging Improvements Enabling Uniformity Of Stacking Process Through Bumpers Wafer level edge stacking Microelectronic Packages And Methods Therefor Stacked packages with bridging traces ...and 275 more
	11/5/2025	International Business Machines Corporat...	Assignor	Application	19377785	Selective Gas Etching For Self-aligned Pattern Transfer
	11/5/2025	Tessera LLC	Assignee	Application	19377785	Selective Gas Etching For Self-aligned Pattern Transfer
	8/20/2025	International Business Machines Corporat...	Assignor	Application	19301725
	8/20/2025	Tessera LLC	Assignee	Application	19301725	Finfet Gate Cut After Dummy Gate Removal
	8/8/2025	International Business Machines Corporat...	Assignor	Application	19276304	Forming Self-aligned Vias And Air-gaps In Semiconductor Fabrication
	8/8/2025	Tessera LLC	Assignee	Application	19276304	Forming Self-aligned Vias And Air-gaps In Semiconductor Fabrication
	8/8/2025	International Business Machines Corporat...	Assignor	Application	19276304	Forming Self-aligned Vias And Air-gaps In Semiconductor Fabrication
	8/8/2025	Tessera LLC	Assignee	Application	19276304	Forming Self-aligned Vias And Air-gaps In Semiconductor Fabrication
	7/31/2025	International Business Machines Corporat...	Assignor	Application	19282431	Air Gap Spacer For Metal Gates
	7/31/2025	Tessera LLC	Assignee	Application	19282431	Air Gap Spacer For Metal Gates
	7/29/2025	International Business Machines Corporat...	Assignor	Application	19259751	Finfet Devices
	7/29/2025	Tessera LLC	Assignee	Application	19259751	Finfet Devices
	7/7/2025	International Business Machines Corporat...	Assignor	Application	19250456	Bulk Nanosheet With Dielectric Isolation
	7/7/2025	Tessera LLC	Assignee	Application	19250456	Bulk Nanosheet With Dielectric Isolation
	7/7/2025	International Business Machines Corporat...	Assignor	Application	19250583	Nanosheet Transistor
	7/7/2025	Tessera LLC	Assignee	Application	19250583	Nanosheet Transistor
	4/24/2025	International Business Machines Corporat...	Assignor	Application Publication	18924834 20250142921	Forming Nanosheet Transistor Using Sacrificial Spacer And Inner Spacers Forming Nanosheet Transistor Using Sacrificial Spacer And Inner Spacers
	4/24/2025	Tessera LLC	Assignee	Application Publication	18924834 20250142921	Forming Nanosheet Transistor Using Sacrificial Spacer And Inner Spacers Forming Nanosheet Transistor Using Sacrificial Spacer And Inner Spacers
	4/24/2025	International Business Machines Corporat...	Assignor	Application Publication	18924834 20250142921	Forming Nanosheet Transistor Using Sacrificial Spacer And Inner Spacers Forming Nanosheet Transistor Using Sacrificial Spacer And Inner Spacers
	4/24/2025	Tessera LLC	Assignee	Application Publication	18924834 20250142921	Forming Nanosheet Transistor Using Sacrificial Spacer And Inner Spacers Forming Nanosheet Transistor Using Sacrificial Spacer And Inner Spacers
	4/14/2025	Tessera LLC	Assignee	Application Publication	19002385 20250140606	Selective Ild Deposition For Fully Aligned Via With Airgap Selective Ild Deposition For Fully Aligned Via With Airgap

50 Rows Total

	Date Recorded	Party	Role	Document Type	Document No.	Image
	6/3/2020	Royal Bank Of Canada	Assignor	Application	86448332
	6/3/2020	Royal Bank Of Canada	Assignor	Application	86568469
	6/3/2020	Royal Bank Of Canada	Assignor	Application	86880068
	6/3/2020	Royal Bank Of Canada	Assignor	Application	85841927
	6/3/2020	Royal Bank Of Canada	Assignor	Application	78525045
	6/3/2020	Royal Bank Of Canada	Assignor	Application	73786916
	6/3/2020	Royal Bank Of Canada	Assignor	Application	74548305
	6/3/2020	Royal Bank Of Canada	Assignor	Application	75907349
	6/3/2020	Royal Bank Of Canada	Assignor	Application	77560790
	6/3/2020	Royal Bank Of Canada	Assignor	Application	77697847
	6/3/2020	Royal Bank Of Canada	Assignor	Application	77857833
	6/3/2020	Royal Bank Of Canada	Assignor	Application	75808170
	6/3/2020	Royal Bank Of Canada	Assignor	Application	78770239
	6/3/2020	Royal Bank Of Canada	Assignor	Application	76978832
	6/3/2020	Royal Bank Of Canada	Assignor	Application	86978348
	6/3/2020	Royal Bank Of Canada	Assignor	Application	75090377
	6/3/2020	Royal Bank Of Canada	Assignor	Application	75659965
	6/3/2020	Royal Bank Of Canada	Assignor	Application	76431526
	6/3/2020	Royal Bank Of Canada	Assignor	Application	85688592
	6/3/2020	Royal Bank Of Canada	Assignor	Application	77288829
	6/3/2020	Royal Bank Of Canada	Assignor	Application	85340289
	6/3/2020	Royal Bank Of Canada	Assignor	Application	86100434
	6/3/2020	Royal Bank Of Canada	Assignor	Application	77945089
	6/3/2020	Royal Bank Of Canada	Assignor	Application	85661270
	6/3/2020	Royal Bank Of Canada	Assignor	Application	74538405
	6/3/2020	Royal Bank Of Canada	Assignor	Application	75218249
	6/3/2020	Royal Bank Of Canada	Assignor	Application	78899459
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	0
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	0
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	5069570
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	0
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	4557635
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	3621008
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	1501111
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	2239286
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	2728752
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	4070942
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	3948347
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	4045995
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	3228983
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	3990915
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	3645101
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	4792103
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	2240960
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	2860944
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	2727566
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	2669755
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	3911403
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	4786034
	6/3/2020	Royal Bank Of Canada	Assignor	Trademark	4543365

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1	3099 Orchard Street San Jose, CA 95134 Get Directions	2	103 Fairview Park Drive Elmsford, Ny 10523 Get Directions
3	3099 Orhcard Drive San Jose, CA 95134 Get Directions	4	3099 Orchard Drive San Jose, CA 95134 Get Directions
5	399 Orchard Drive San Jose, CA 95134 Get Directions	6	3099 Orchard Drive San Jose, CA 85134 Get Directions
7	3025 ORCHARD PARKWAY ATTN.: IP LEGAL DEPARTMENT SAN JOSE, CA 95134 Get Directions	8	3299 Orchard Drive San Jose, CA 95134 Get Directions
9	San Jose, CA 95134 Get Directions	10	119 1st Avenue South Suite 410 Seattle, WA 98104 Get Directions
11	103 Fairview Park Dr Elmsford, NY 10523 Get Directions	12	3099 Orchard Drive, San Jose, Ca 95134 , CA Get Directions
13	3099 Orchard Parkway San Jose, CA 95134 Get Directions	14	3099 Orchard Drive San Francisco, CA 94134 Get Directions
15	c/o Christopher Lattin 2702 Orchard Parkway San Jose, CA 95134 Get Directions	16	3025 Orchard Parkway San Jose, CA 95134 Get Directions
17	3099 Orchard Dr A Delaware Corporation San Jose, CA 95134 Get Directions	18	3099 Orchard Drive Delaware Corporation San Jose, CA 95134 Get Directions
19	3099 Orchard Drive San Jose, CA 95123 Get Directions	20	3025 Orchard Parkway San Jose, CA USA 95134 Get Directions
21	103 Fairview Park Drive Elmsford, NE 10523 Get Directions